MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 103

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Freescale Semiconductor
Note:
1. Multi-pin signals such as D1_MDQ[0:63] and D2_MDQ[0:63] have their physical package pin numbers listed in order
2. Stub Series Terminated Logic (SSTL-18 and SSTL-25) type pins.
3. If a DDR port is not used, it is possible to leave the related power supply (Dn_GVDD, Dn_MVREF) turned off at reset. Note
4. Low Voltage Differential Signaling (LVDS) type pins.
5. Low Voltage Transistor-Transistor Logic (LVTTL) type pins.
6. This pin is a reset configuration pin and appears again in the Reset Configuration Signals section of this table. See the Reset
7. Recommend a weak pull-up resistor (1–10 kΩ) be placed from this pin to its power supply.
8. Recommend a weak pull-down resistor (2–10 kΩ) be placed from this pin to ground.
9. This multiplexed pin has input status in one mode and output in another
10. This pin is a multiplexed signal for different functional blocks and appears more than once in this table.
11. This pin is open drain signal.
12. Functional only on the MPC8640D.
13. These pins should be left floating.
14. These pins should be connected to SV
15. These pins should be pulled to ground with a strong resistor (270-Ω to 330-Ω).
16. These pins should be connected to OVDD.
17.This is a SerDes PLL/DLL digital test signal and is only for factory use.
18. This is a SerDes PLL/DLL analog test signal and is only for factory use.
19. This pin should be pulled to ground with a 100-Ω resistor.
20. The pins in this section are reset configuration pins. Each pin has a weak internal pull-up P-FET which is enabled only when
21. Should be pulled down at reset if platform frequency is at 400 MHz.
22. These pins require 4.7-kΩ pull-up or pull-down resistors and must be driven as they are used to determine PLL configuration
23. This output is actively driven during reset rather than being released to high impedance during reset.
24 These JTAG pins have weak internal pull-up P-FETs that are always enabled.
25. This pin should NOT be pulled down (or driven low) during reset.
26.These are test signals for factory use only and must be pulled up (100-Ω to 1- kΩ.) to OVDD for normal machine operation.
27. Dn_MDIC[0] should be connected to ground with an 18-Ω resistor ± 1-Ω and Dn_MDIC[1] should be cLonnected Dn_GVDD
28. Pin N18 is recommended as a reference point for determining the voltage of V
29. Pin P18 is recommended as the ground reference point for SENSEVDD_PLAT and is called SENSEVSS_PLAT.
30.This pin should be pulled to ground with a 200-Ω resistor.
31.These pins are connected to the power/ground planes internally and may be used by the core power supply to improve
32. Must be tied low if unused
33. These pins may be used as defined functional reset configuration pins in the future. Please include a resistor pull-up/down
34. Used as serial data output for serial RapidIO 1×/4× link.
35. Used as serial data input for serial RapidIO 1×/4× link.
36.This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively
corresponding to the signal names.
that these power supplies can only be powered up again at reset for functionality to occur on the DDR port.
Configuration Signals section of this table for config name and connection details.
the processor is in the reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down
resistor. However, if the signal is intended to be high after reset, and if there is any device on the net which might pull down
the value of the net at reset, then a pullup or active driver is needed.
ratios at reset.
with an 18-Ω resistor ± 1-Ω. These pins are used for automatic calibration of the DDR IOs.
V
tracking and regulation.
option to allow flexibility of future designs.
driven.
DD
_PLAT sensing voltage and is called SENSEVDD_PLAT.
Name
1
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Table 63. MPC8640 Signal Reference by Functional Block (continued)
Package Pin Number
DD
.
Pin Type
DD
_PLAT and is hence considered as the
Power Supply
Signal Listings
Notes
103