MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 56

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

I
Figure 32
56
All values refer to V
2
Noise margin at the HIGH level for each connected device (including
hysteresis)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. As a transmitter, the MPC8640 provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL
3. The maximum t
4. Guaranteed by design.
5. C
C
for inputs and t
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
high (H) state or setup time. Also, t
(S) went invalid (X) relative to the t
timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.
When MPC8640 acts as the I
SCL and SDA are balanced, MPC8640 would not cause unintended generation of Start or Stop condition. Therefore, the 300
ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required for
MPC8640 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure both the
desired I
is 400 KHz and the Digital Filter Sampling Rate Register (I2CDFSRR) is programmed with its default setting of 0x10 (decimal
16):
For the detail of I
for SCL.” Note that the I
B
= capacitance of one bus line in pF.
I
FDR Bit Setting
Actual FDR Divider Selected
Actual I
2
C Source Clock Frequency
2
provides the AC test load for the I
C SCL clock frequency and SDA output delay time are achieved, assuming that the desired I
2
C SCL Frequency Generated
IH
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
I2DXKL
(min) and V
2
C frequency calculation, refer to the application note AN2919 “Determining the I
has only to be met if the device does not stretch the LOW period (t
2
Output
C Source Clock Frequency is half of the MPX clock frequency for MPC8640.
Parameter
IL
Table 46. I
(max) levels (see
2
C bus master while transmitting, MPC8640 drives both SCL and SDA. As long as the load on
I2SXKL
I2C
clock reference (K) going to the low (L) state or hold time. Also, t
symbolizes I
2
C AC Electrical Specifications (continued)
Figure 36. I
Table
371 KHz
333 MHz
0x2A
896
Z
0
= 50 Ω
45).
2
C.
2
C timing (I2) for the time that the data with respect to the start condition
2
266 MHz
0x05
704
378 KHz
C AC Test Load
for outputs. For example, t
Symbol
(first two letters of functional block)(signal)(state) (reference)(state)
200 MHz
0x26
512
390 KHz
V
NH
R
L
1
= 50 Ω
0.2 × OV
133 MHz
0x00
384
346 KHz
Min
I2C
OV
I2CL
DD
clock reference (K) going to the
DD
) of the SCL signal.
I2DVKH
/2
2
C Frequency Divider Ratio
Freescale Semiconductor
2
C SCL clock frequency
I2PVKH
symbolizes I
Max
—
symbolizes I
2
I2C
C timing
Unit
clock
V
2
C