MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 76

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Serial RapidIO
To ensure interoperability between drivers and receivers of different vendors and technologies, AC
coupling at the receiver input must be used.
15.1
For more information, see
15.2
Table 51
15.3
LP-Serial links use differential signaling. This section defines terms used in the description and
specification of differential signals.
waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each signal
swings between A volts and B volts where A > B. Using these waveforms, the definitions are as follows:
76
Symbol
t
t
REFCJ
REFPJ
t
REF
1. The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a
2. The differential output signal of the transmitter, V
3. The differential input signal of the receiver, V
4. The differential output signal of the transmitter and the differential input signal of the receiver
peak-to-peak swing of A – B volts
each range from A – B to –(A – B) volts
REFCLK cycle time
REFCLK cycle-to-cycle jitter. Difference in the
period of any two adjacent REFCLK cycles
Phase jitter. Deviation in edge location with
respect to mean edge location
lists AC requirements.
DC Requirements for Serial RapidIO SD n _REF_CLK and
SD n _REF_CLK
AC Requirements for Serial RapidIO SD n _REF_CLK and
SD n _REF_CLK
Signal Definitions
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Parameter Description
Table 51. SD n _REF_CLK and SD n _REF_CLK AC Requirements
Section 13.2, “SerDes Reference Clocks.”
Figure 53
shows how the signals are defined. The figures show
Min
–40
—
—
ID
Typical Max Units
10(8)
, is defined as V
—
—
OD
, is defined as V
80
40
—
ns
ps
ps
RD
8 ns applies only to serial RapidIO
with 125-MHz reference clock
– V
TD
RD
– V
TD
Freescale Semiconductor
Comments
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