MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 73

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

14.5
The Rx eye diagram in
Figure
Note that in general, the minimum receiver eye diagram measured with the compliance/test measurement
load (see
the input receiver of any real PCI Express component. The degraded eye diagram at the input receiver is
due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI
Express component to vary in impedance from the compliance/test measurement load. The input receiver
eye diagram is implementation specific and is not specified. A Rx component designer should provide
Freescale Semiconductor
Unexpected
Electrical Idle
Enter Detect
Threshold
Integration Time
Total Skew
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in
3. A T
4. The receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased to
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
6. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
7. It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
as the Rx device when taking measurements (also refer to the Receiver compliance eye diagram shown in
clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
interconnect collected any 250 consecutive UIs. The T
which the median and the maximum deviation from the median is less than half of the total. UI jitter budget collected over any
250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median describes the point
in time where the number of jitter points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must
be used as the reference for the eye diagram.
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured by
a vector network analyzer with 50-Ω probes, see
measurement.
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
ensure that the receiver detect circuit will not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the Rx ground.
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and simulated
data.
Parameter
RX-EYE
52) in place of any real PCI Express Rx component.
Figure
Receiver Compliance Eye Diagrams
= 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
T
ENTERTIME
L
TX-SKEW
RX-IDLE-DET-DIFF-
52) is larger than the minimum receiver eye diagram measured over a range of systems at
Symbol
Table 50. Differential Receiver Input Specifications (continued)
Figure 51
is specified using the passive compliance/test measurement load (see
Min
—
—
Figure
Nom
—
—
RX-EYE-MEDIAN-to-MAX-JITTER
52). Note that the series capacitors C
Max
10
20
Units
ms
ns
An unexpected electrical Idle (V
V
longer than T
signal an unexpected idle condition.
Skew across all lanes on a link. This includes
variation in the length of SKP ordered set (for
example, COM and one to five symbols) at
the Rx as well as any delay differences arising
from the interconnect itself.
RX-IDLE-DET-DIFFp-p
specification ensures a jitter distribution in
RX-IDLE-DET-DIFF-ENTERING
TX
is optional for the return loss
Comments
Figure 52
) must be recognized no
Figure
should be used
RX-DIFFp-p
PCI Express
51). If the
to
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