MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 105

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

18.2
The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency
of the MPX is set using the following reset signals, as shown in
Freescale Semiconductor
Memory bus clock frequency
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
2. The memory bus clock speed is half the DDR/DDR2 data rate, hence, half the MPX clock frequency.
Platform/MPX bus clock frequency
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
2. Platform/MPX frequencies between 400 and 500 MHz are not supported.
Local bus clock speed (for Local Bus Controller)
Notes:
1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus PLL ratio programmed in
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
for ratio settings.
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
for ratio settings.
LCRR[CLKDIV]. See the reference manual for the MPC8641D for more information on this.
•
SYSCLK input signal
MPX to SYSCLK PLL Ratio
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Parameter
Parameter
Parameter
Table 66. Platform/MPX bus Clocking Specifications
Section 18.2, “MPX to SYSCLK PLL Ratio,”
Section 18.2, “MPX to SYSCLK PLL Ratio,”
Table 65. Memory Bus Clocking Specifications
Table 67. Local Bus Clocking Specifications
Maximum Processor Core
Maximum Processor Core
Maximum Processor Core
Min
200
Min
400
Min
1000, 1067, 1250 MHz
1000, 1067, 1250 MHz
1000, 1067, 1250 MHz
25
Frequency
Frequency
Frequency
and
and
Table
Section 18.3, “e600 to MPX clock PLL Ratio,”
Section 18.3, “e600 to MPX clock PLL Ratio,”
68:
Max
Max
Max
266
533
133
Unit
MHz
MHz
MHz
Unit
Unit
Notes
Notes
Notes
1, 2
1, 2
Clocking
1
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