MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 4

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Overview
4
•
•
•
•
•
DDR memory controllers
— Dual 64-bit memory controllers (72-bit with ECC)
— Support of up to a 266 MHz clock rate and a 533 MHz DDR2 SDRAM
— Support for DDR, DDR2 SDRAM
— Up to 16 Gbytes per memory controller
— Cache line and page interleaving between memory controllers.
Serial RapidIO interface unit
— Supports RapidIO Interconnect Specification, Revision 1.2
— Both 1× and 4× LP-Serial link interfaces
— Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per
— Message unit compliant with RapidIO specifications
— RapidIO atomic transactions to the memory controller
PCI Express interface
— PCI Express 1.0a compatible
— Supports ×1, ×2, ×4, and ×8 link widths
— 2.5 Gbaud, 2.0 Gbps lane
Four enhanced three-speed Ethernet controllers (eTSECs)
— Three-speed support (10/100/1000 Mbps)
— Four controllers that comply with IEEE Std. 802.3®, 802.3u®, 802.3x®, 802.3z®, 802.3ac®,
— Support for the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI
— Support for a full-duplex FIFO mode for high-efficiency ASIC connectivity
— TCP/IP off-load
— Header parsing
— Quality of service support
— VLAN insertion and deletion
— MAC address recognition
— Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III
— RMON statistics support
— MII management interface for control and status
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts and 48 internal interrupts
— Eight global high resolution timers/counters that can generate interrupts
lane
802.3ab® standards
programming models
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Freescale Semiconductor