MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 16

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

At recommended operating conditions (see
Input Clocks
4.1.1
Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference
emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise
magnitude in order to meet industry and government requirements. These clock sources intentionally add
long-term jitter to diffuse the EMI spectral content. The jitter specification given in
short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter should meet the
MPC8640 input cycle-to-cycle jitter requirement. Frequency modulation and spread are separate concerns,
and the MPC8640 is compatible with spread spectrum sources if the recommendations listed in
observed.
At recommended operating conditions. See
It is imperative to note that the processor’s minimum and maximum SYSCLK, core, and VCO frequencies
must not be exceeded regardless of the type of clock source. Therefore, systems in which the processor is
operated at its maximum rated e600 core frequency should avoid violating the stated limits by using
down-spreading only.
SDn_REF_CLK and SDn_REF_CLK were designed to work with a spread spectrum clock (+0 to 0.5%
spreading at 30-33 kHz rate is allowed), assuming both ends have same reference clock. For better results,
use a source without significant unintended modulation.
16
SYSCLK duty cycle
SYSCLK jitter
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
2. Rise and fall times for SYSCLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the short term jitter only and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to allow
Frequency modulation
Frequency spread
Notes:
1. Guaranteed by design.
2. SYSCLK frequencies resulting from frequency spreading, and the resulting core and VCO frequencies, must meet the
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to
Ratio,”
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter. Note that the frequency modulation
for SYSCLK reduces significantly for the spread spectrum source case. This is to guarantee what is supported based on
design.
minimum and maximum specifications given in
for ratio settings.
SYSCLK and Spread Spectrum Sources
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Parameter
Table 9. Spread Spectrum Clock Source Recommendations
Parameter
Table 8. SYSCLK AC Timing Specifications (continued)
Section 18.2, “MPX to SYSCLK PLL Ratio,”
Table
Table
2.
2) with OV
Table
t
KHK
Symbol
/t
—
8.
SYSCLK
DD
= 3.3 V ± 165 mV
Min
40
—
Min
—
—
and
.
Typical
Section 18.3, “e600 to MPX clock PLL
—
—
Max
1.0
50
Max
150
60
Table 8
Freescale Semiconductor
Unit
kHz
%
Unit
ps
%
considers
Table 9
Notes
Notes
1, 2
4, 5
1
3
are