MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 61

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

13.2.2
The DC level requirement for the MPC8640D SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
Freescale Semiconductor
•
•
SD n _REF_CLK
SD n _REF_CLK
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
— For external DC-coupled connection, as described in section 13.2.1, the maximum average
— For external AC-coupled connection, there is no common mode voltage requirement for the
Single-ended Mode
— The reference clock can also be single-ended. The SDn_REF_CLK input amplitude
— The SDn_REF_CLK input average voltage must be between 200 and 400 mV.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled)
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800 mV and
greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
current requirements sets the requirement for average voltage (common mode voltage) to be
between 100 mV and 400 mV.
for DC-coupled connection scheme.
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND. Each signal wire of the differential inputs is allowed to swing below and above the
command mode voltage (SGND).
requirement for AC-coupled connection scheme.
(single-ended swing) must be between 400 mV and 800 mV peak-peak (from V
with SDn_REF_CLK either left unconnected or tied to ground.
the SerDes reference clock input requirement for single-ended signaling mode.
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
DC Level Requirement for SerDes Reference Clocks
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
200mV < Input Amplitude or Differential Peak < 800mV
Figure 40
Figure 41
shows the SerDes reference clock input requirement
shows the SerDes reference clock input
High-Speed Serial Interfaces (HSSI)
100mV < Vcm < 400mV
Vmax < 800mV
Vmin > 0V
Figure 42
min
to V
shows
max
)
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