MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 53

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Figure 32
Figure 33
Freescale Semiconductor
At recommended operating conditions (see
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
for inputs and t
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. Also, t
data input signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
provides the AC test load for TDO and the boundary-scan outputs.
provides the JTAG clock input timing diagram.
Table 44. JTAG AC Timing Specifications (Independent of SYSCLK)
External Clock
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
(first two letters of functional block)(reference)(state)(signal)(state)
Parameter
JTAG
Output
Figure 32. AC Test Load for the JTAG Interface
Figure 33. JTAG Clock Input Timing Diagram
Boundary-scan data
Boundary-scan data
Table
VM
t
JTKHKL
3).
Z
VM = Midpoint Voltage (OV DD /2)
0
TCLK
t
= 50 Ω
JTG
TCLK
TDO
TDO
.
VM
JTG
.
clock reference (K) going to the high (H) state. Note that, in general,
Symbol
t
t
t
t
JTKLDX
JTKLOX
JTKLOZ
JTKLDZ
JTDXKH
VM
2
for outputs. For example, t
symbolizes JTAG timing (JT) with respect to the time
(first two letters of functional block)(signal)(state) (reference)(state)
R
L
= 50 Ω
Min
TCLK
30
30
t
3
3
JTGR
to the midpoint of the signal in question.
OV
Max
DD
—
—
19
1
t
9
JTGF
/2
(continued)
JTDVKH
symbolizes JTAG
Unit
ns
ns
Figure
JTG
clock
32).
Notes
5, 6
5, 6
JTAG
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