MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 33

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

At recommended operating conditions with L/TV
Figure 14
Figure 15
8.2.4
This section describes the TBI transmit and receive AC timing specifications.
Freescale Semiconductor
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise time (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. Guaranteed by design.
3. ±100 ppm tolerance on RX_CLK frequency
for inputs and t
timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
going to the high (H) state or setup time. Also, t
signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For
example, the subscript of t
with the appropriate letter: R (rise) or F (fall).
provides the AC test load for eTSEC.
shows the MII receive AC timing diagram.
TBI AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
RXD[3:0]
RX_CLK
RX_DV
RX_ER
Parameter
Output
Table 31. MII Receive AC Timing Specifications (continued)
MRX
represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used
Figure 15. MII Receive AC Timing Diagram
t
t
MRXH
MRDVKH
DD
MRX
Figure 14. eTSEC AC Test Load
of 3.3 V ± 5%.
t
MRX
clock reference (K) going to the low (L) state or hold time. Note that, in general,
Z
MRDXKL
0
= 50 Ω
Valid Data
symbolizes MII receive timing (GR) with respect to the time data input
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
Symbol
t
t
t
MRXF
MRDVKH
MRDXKH
t
t
MRXR
MRXF
for outputs. For example, t
2
2
(first two letters of functional block)(signal)(state) (reference)(state)
1
R
t
MRDXKL
t
L
MRXR
= 50 Ω
10.0
10.0
Min
1.0
1.0
LV
DD
Typ
MRDVKH
—
—
—
—
/2
MRX
symbolizes MII receive
clock reference (K)
Max
4.0
4.0
—
—
Unit
ns
ns
ns
ns
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