MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 119

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

20.5.1
This section provides the guidelines for high-speed interface termination.
20.5.1.1
The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:3] and through the
DEVDISR register in software. If a SerDes port is disabled through the POR input the user cannot enable
it through the DEVDISR register in software. However, if a SerDes port is enabled through the POR input
the user can disable it through the DEVDISR register in software. Disabling a SerDes port through
software should be done on a temporary basis. Power is always required for the SerDes interface, even if
the port is disabled through either mechanism.
for a SerDes port. The termination recommendations must be followed for each port.
If the high-speed SerDes port requires complete or partial termination, the unused pins should be
terminated as described in this section.
Freescale Semiconductor
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Note:
Disabled through DEVDISR
Partial Termination when a SerDes port is enabled through both POR input and DEVDISR is determined by the SerDes
port mode. If the port is in ×8 PCI Express mode, no termination is required because all pins are being used. If the port
is in ×1/×2/×4 PCI Express mode, termination is required on the unused pins. If the port is in ×4 serial RapidIO mode,
termination is required on the unused pins.
If a SerDes port is enabled through the POR input and then disabled through DEVDISR, no hardware changes are
required. Termination of the SerDes port should follow what is required when the port is enabled through both POR
input and DEVDISR. See Note 1 for more information.
Enabled through DEVDISR
Local Bus—If parity is not used, tie LDP[0:3] to ground via a 4.7-kΩ resistor, tie LPBSE to OV
via a 4.7-kΩ resistor (pull-up resistor). For systems which boot from Local Bus
(GPCM)-controlled flash, a pull-up on LGPL4 is required.
SerDes—Receiver lanes configured for PCI Express are allowed to be disconnected (as would
occur when a PCI Express slot is connected but not populated). Directions for terminating the
SerDes signals is discussed in
Guidelines for High-Speed Interface Termination
SerDes Interface
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Table 72. SerDes Port Enabled/Disabled Configurations
SerDes port is disabled (and cannot
SerDes port is disabled (through
Disabled Through POR Input
be enabled through DEVDISR)
(Reference Clock not required)
(Reference Clock not required)
Complete termination required
Complete termination required
Section 20.5.1, “Guidelines for High-Speed Interface
POR input)
Table 72
describes the possible enabled/disabled scenarios
Same termination requirements as when the
SerDes port is disabled after software
Partial termination may be required
port is enabled through POR input
Enabled Through POR Input
(Reference Clock is required)
(Reference Clock is required)
SerDes port is enabled
disables port
System Design Information
Termination.”
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