MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 123

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

The COP interface has a standard header, shown in
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header shown in
pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 67
For a multi-processor non-daisy chain configuration,
recommended daisy chain configuration is shown in
determine which configuration is supported by their emulator.
20.9.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
Freescale Semiconductor
•
•
•
TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in
in case a JTAG interface may need to be wired onto the system in future debug situations.
Tie TCK to OV
reading incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
is common to all known emulators.
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Figure
DD
COP_CHKSTP_OUT
through a 10 kΩ resistor. This will prevent TCK from changing state and
68. If this is not possible, the isolation resistor will allow future access to TRST
COP_HRESET
COP_SRESET
Figure 67. COP Connector Physical Pinout
COP_TDO
COP_TMS
COP_TCK
COP_TDI
NC
13
15
11
1
1
3
5
7
9
No pin
Figure
KEY
Figure
Figure
10
12
16
2
4
6
8
67, for connection to the target system, and is
68, can be duplicated for each processor. The
69. Please consult with your tool vendor to
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
NC
GND
Figure
67; consequently, many different
System Design Information
123