MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 116

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

System Design Information
20 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8640.
20.1
This device includes six PLLs, as follows:
20.2
This section describes the power supply design and sequencing.
20.2.1
Each of the PLLs listed in
power supply pins.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits per PLL power supply as illustrated in
AV
from one PLL to the other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
type pin, which is on the periphery of the footprint, without the inductance of vias.
Figure 63
116
DD
•
•
•
•
V
DD
type pins. By providing independent filters to each PLL the opportunity to cause noise injection
The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in
The dual e600 Core PLLs generate the e600 clock from the externally supplied input.
The local bus PLL generates the clock for the local bus.
There are two internal PLLs for the SerDes block.
_PLAT
System Clocking
Power Supply Design and Sequencing
and
PLL Power Supply Filtering
Figure 63. MPC8640 PLL Power Supply Filter Circuit (for platform and Local Bus)
Figure 64
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
10 Ω
show the PLL power supply filter circuits for the platform and cores, respectively.
Section 20.1, “System Clocking,”
2.2 µF
GND
Section 18.2, “MPX to SYSCLK PLL Ratio.”
2.2 µF
Low ESL Surface Mount Capacitors
is provided with power through independent
AV
DD
_PLAT, AV
DD
type pin being supplied to minimize
Figure
DD
_LB;
64, one to each of the
Freescale Semiconductor
DD