MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 118

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

System Design Information
designer place at least one decoupling capacitor at each OV
and V
OV
utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a
standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the OV
recharging of the smaller chip capacitors. They should also be connected to the power and ground planes
through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum
or Sanyo OSCON).
20.4
The SerDes block requires a clean, tightly regulated source of power (SV
low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling scheme is
outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
20.5
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. In general all unused active low inputs should be tied to OV
V
be connected to GND. All NC (no-connect) signals must remain unconnected.
The following list explains the special cases:
118
DD
DD
•
•
•
•
_Coren, and V
DD
, Dn_GV
First, the board should have at least 10 × 10-nF SMT ceramic chip capacitors as close as possible
to the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-µF ceramic chip capacitor on each side of the device. This should be
done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-µF, low
equivalent series resistance (ESR) SMT tantalum chip capacitor and a 100-µF, low ESR SMT
tantalum chip capacitor. This should be done for all SerDes supplies.
DDR—If one of the DDR ports is not being used the power supply pins for that port can be
connected to ground so that there is no need to connect the individual unused inputs of that port to
ground. Note that these power supplies can only be powered up again at reset for functionality to
occur on the DDR port. Power supplies for other functional buses should remain powered.
_PLAT pin of the device. These decoupling capacitors should receive their power from separate
Connection Recommendations
SerDes Block Power Supply Decoupling Recommendations
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
DD
DD
, Dn_GV
, LV
DD
_PLAT, XV
DD
, TV
DD
DD
, LV
, V
DD
DD
DD
_SRDSn, and SV
, TV
_Coren, and V
DD
, V
DD
_Coren, and V
DD
DD
_PLAT and GND power planes in the PCB,
as required and unused active high inputs should
DD
, Dn_GV
DD
DD
_PLAT planes, to enable quick
, Dn_GV
DD
DD
, LV
and XV
DD
DD
, LV
, TV
DD
Freescale Semiconductor
DD
_SRDSn) to ensure
DD
, TV
, V
DD
DD
_Coren,
,