MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 17

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

4.2
The RTC input is sampled by the platform clock (MPX clock). The output of the sampling latch is then
used as an input to the counters of the PIC. There is no jitter specification. The minimum pulse width of
the RTC signal should be greater than 2× the period of the MPX clock. That is, minimum clock high time
is 2 × t
grounded if not needed.
4.3
Table 10
timing specifications for the MPC8640.
4.4
The MPX platform clock frequency must be considered for proper operation of the high-speed PCI
Express and Serial RapidIO interfaces as described below.
For proper PCI Express operation, the MPX clock frequency must be greater than or equal to:
Freescale Semiconductor
EC n _GTX_CLK125 frequency
EC n _GTX_CLK125 cycle time
EC n _GTX_CLK125 peak-to-peak jitter
EC n _GTX_CLK125 duty cycle
Notes:
1. Timing is guaranteed by design and characterization.
2. EC n _GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. EC n _GTX_CLK125
3. ±100 ppm tolerance on EC n _GTX_CLK125 frequency.
duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated by the eTSEC
GTX_CLK. See
reference clock.
MPX
provides the eTSEC gigabit reference clocks (EC1_GTX_CLK125 and EC2_GTX_CLK125) AC
Real Time Clock Timing
eTSEC Gigabit Reference Clock Timing
Platform Frequency Requirements for PCI-Express and Serial
RapidIO
, and minimum clock low time is 2 × t
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
Parameter
1000Base-T for RGMII, RTBI
Section 8.2.6, “RGMII and RTBI AC Timing Specifications,”
Table 10. EC n _GTX_CLK125 AC Timing Specifications
GMII, TBI
527 MHz x (PCI-Express link width)
t
16 / (1 + cfg_plat_freq)
G125H
Symbol
t
f
t
G125J
G125
G125
/t
MPX
G125
NOTE
. There is no minimum RTC frequency; RTC may be
Min
—
—
—
45
47
for duty cycle for 10Base-T and 100Base-T
125 ± 100
Typical
ppm
—
—
8
Max
250
55
53
—
—
Unit
MHz
ns
ps
%
Input Clocks
Notes
1, 2
—
3
1
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