MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 23

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

At recommended operating conditions (see
Freescale Semiconductor
MDQ/MECC/MDM output setup with respect to
MDQS
MDQ/MECC/MDM output hold with respect to
MDQS
MDQS preamble start
MDQS epilogue end
Note:
1. The symbols used for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that t
7. Maximum DDR1 frequency is 400 MHz
8. Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values.
inputs and t
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
t
outputs (A) are setup (S) or output valid time. Also, t
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t
control of the DQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This will typically be set to the
same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2
parameters have been set to the same adjustment value. See the MPC8641 Integrated Processor Reference Manual for a
description and understanding of the timing modifications enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHAS
symbolizes DDR timing (DD) for the time t
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
For the ADDR/CMD setup and hold specifications in
assumed that the Clock Control register is set to adjust the memory clocks
by 1/2 applied cycle.
Parameter
follows the symbol conventions described in note 1. For example, t
Table 21. DDR SDRAM Output AC Timing Specifications (continued)
Table
533 MHz
400 MHz
533 MHz
400 MHz
2).
Symbol
t
t
t
t
t
t
DDKHDS,
DDKHDX,
DDKHMP
DDKHME
MCK
DDKLDS
DDKLDX
DDKLDX
memory clock reference (K) goes from the high (H) state until
NOTE
1
symbolizes DDR timing (DD) for the time t
(first two letters of functional block)(signal)(state) (reference)(state)
–0.5 × t
for outputs. Output hold time can be read as DDR timing
–0.6
Min
590
700
590
700
MCK
– 0.6
Table
DDKHMH
–0.5 × t
21, it is
DDKHMH
Max
0.6
—
—
—
—
MCK
describes the DDR timing
can be modified through
+0.6
DDKHMP
DDR and DDR2 SDRAM
MCK
memory clock
Unit
follows the
ps
ps
ns
ns
Notes
for
5
7
5
7
6
6
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