MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 42

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Ethernet Management Interface Electrical Characteristics
At recommended operating conditions with OV
Figure 23
Figure 24
42
MDC fall time
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is
4. Guaranteed by design.
5. t
for inputs and t
management data timing (MD) for the time t
hold time. Also, t
valid state (V) relative to the t
latter convention is used with the appropriate letter: R (rise) or F (fall).
divided by 64.)
8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and
the minimum frequency is 1.7 MHz.)
MPXCLK
is the platform (MPX) clock
provides the AC test load for eTSEC.
shows the MII management AC timing diagram.
Parameter
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
(first two letters of functional block)(reference)(state)(signal)(state)
Output will see a 50 Ω load since what it sees is the transmission line.
MDDVKH
(Output)
(Input)
MDIO
MDIO
MDC
Table 39. MII Management AC Timing Specifications (continued)
Output
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
Figure 24. MII Management Interface Timing Diagram
MDC
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
t
MDCH
DD
Symbol
t
t
MDDVKH
is 3.3 V ± 5%.
MDHF
Figure 23. eTSEC AC Test Load
MDC
t
MDC
Z
t
MDKHDX
0
1
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
= 50 Ω
NOTE
Min
—
t
MDCF
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
t
MDDXKH
R
Typ
—
t
L
MDCR
= 50 Ω
OV
Max
10
DD
/2
MDKHDX
Freescale Semiconductor
symbolizes
Unit
ns
Notes
4