MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 35

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

Figure 16
8.2.4.2
Table 33
Freescale Semiconductor
At recommended operating conditions with L/TV
PMA_RX_CLK[0:1] clock period
PMA_RX_CLK[0:1] skew
PMA_RX_CLK[0:1] duty cycle
RCG[9:0] setup time to rising PMA_RX_CLK
RCG[9:0] hold time to rising PMA_RX_CLK
PMA_RX_CLK[0:1] clock rise time (20%–80%)
PMA_RX_CLK[0:1] clock fall time (80%–20%)
Note:
1. The symbols used for timing specifications herein follow the pattern of t
2. Guaranteed by design.
3. ±100 ppm tolerance on PMA_RX_CLK[0:1] frequency
for inputs and t
receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to the t
(K) going to the high (H) state or setup time. Also, t
input signals (D) went invalid (X) relative to the t
clock reference symbol representation is based on three letters representing the clock of a particular functional. For example,
the subscript of t
appropriate letter: R (rise) or F (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that
is being skewed (TRX).
provides the TBI receive AC timing specifications.
shows the TBI transmit AC timing diagram.
TBI Receive AC Timing Specifications
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
(first two letters of functional block)(reference)(state)(signal)(state)
GTX_CLK
TCG[9:0]
TRX
represents the TBI (T) receive (RX) clock. For rise and fall times, the latter convention is used with the
Parameter
Table 33. TBI Receive AC Timing Specifications
Figure 16. TBI Transmit AC Timing Diagram
t
TTXH
t
TTKHDV
t
DD
TTXF
of 3.3 V ± 5% and 2.5 V ± 5%.
t
TTX
TRX
TRDXKH
clock reference (K) going to the high (H) state. Note that, in general, the
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
symbolizes TBI receive timing (TR) with respect to the time data
t
Symbol
TRXH
t
t
t
TRDXKH
t
TRDVKH
t
TTXF
t
SKTRX
TRXR
t
TRXF
TRX
/t
3
TRX
2
for outputs. For example, t
2
(first two letters of functional block)(signal)(state) (reference)(state)
1
t
TTKHDX
t
TTXR
Min
7.5
2.5
1.5
0.7
0.7
40
—
t
TTXR
16.0
Typ
—
—
—
—
—
—
TRDVKH
symbolizes TBI
TRX
Max
8.5
2.4
2.4
60
—
—
—
clock reference
Unit
ns
ns
ns
ns
ns
ns
%
35