MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 28

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

At recommended operating conditions with L/TV
Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management
clock to synchronously generate transmit data and outputs an echoed copy of the transmit clock back out
onto the TSECn_GTX_CLK pin (while transmit data appears on TSECn_TXD[7:0], for example). It is
intended that external receivers capture eTSEC transmit data using the clock on TSECn_GTX_CLK as a
source- synchronous timing reference. Typically, the clock edge that launched the data can be used, since
the clock is delayed by the eTSEC to allow acceptable set-up margin at the receiver. Note that there is
relationship between the maximum FIFO speed and the platform speed. For more information, see
Section 18.4.2, “Platform to FIFO
A summary of the FIFO AC specifications appears in
At recommended operating conditions with L/TV
28
TX_CLK, GTX_CLK clock period (GMII mode)
TX_CLK, GTX_CLK clock period (Encoded mode)
TX_CLK, GTX_CLK duty cycle
TX_CLK, GTX_CLK peak-to-peak jitter
Rise time TX_CLK (20%–80%)
Fall time TX_CLK (80%–20%)
FIFO data TXD[7:0], TX_ER, TX_EN setup time to
GTX_CLK
GTX_CLK to FIFO data TXD[7:0], TX_ER, TX_EN hold
time
RX_CLK clock period (GMII mode)
RX_CLK clock period (Encoded mode)
RX_CLK duty cycle
RX_CLK peak-to-peak jitter
Rise time RX_CLK (20%–80%)
Fall time RX_CLK (80%–20%)
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
The phase between the output clocks TSEC1_GTX_CLK and
TSEC2_GTX_CLK (ports 1 and 2) is no more than 100 ps. The phase
between the output clocks TSEC3_GTX_CLK and TSEC4_GTX_CLK
(ports 3 and 4) is no more than 100 ps.
Parameter
Parameter
Table 26. FIFO Mode Transmit AC Timing Specification
Table 27. FIFO Mode Receive AC Timing Specification
Restrictions.”
DD
DD
of 3.3 V ± 5% and 2.5 V ± 5%.
of 3.3 V ± 5% and 2.5 V ± 5%.
NOTE
t
Symbol
t
Symbol
FIRH
FITH/
t
t
t
t
t
t
FITDX
t
t
t
FIRDV
FIRDX
t
FITDV
t
t
FIR
FITR
FIRR
FIRF
t
t
FITF
FIR
FIRJ
FITJ
FIT
FIT
Table 26
/t
t
1
FIT
1
FIR
and
Min
Min
8.4
6.4
1.5
0.5
8.4
6.4
2.0
0.5
45
45
—
—
—
—
—
—
Table
27.
Typ
Typ
8.0
8.0
8.0
8.0
50
50
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Max
0.75
0.75
Max
0.75
0.75
100
100
250
100
100
250
3.0
55
55
—
—
—
Unit
Unit
ns
ns
ps
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
%
%