MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 60

• Manufacturer Part Number: MC8640DTHX1067NE
• Description: IC MPU DUAL CORE E600 1023FCCBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC8640DTHX1067NE

• Processor Type: MPC86xx PowerPC 32-Bit
• Speed: 1.067GHz
• Voltage: 0.95V
• Mounting Type: Surface Mount
• Package / Case: 1023-FCCBGA
• Processor Series: MPC8xxx
• Core: e600
• Development Tools By Supplier: MCEVALHPCN-8641D
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No

High-Speed Serial Interfaces (HSSI)
13.2.1
Figure 39
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The supply voltage requirements for XV
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
The input amplitude requirement
— This requirement is described in detail in the following sections.
shows a receiver reference diagram of the SerDes reference clocks.
shown in
50-Ω termination to SGND followed by on-chip AC-coupling.
Differential Mode and Single-ended Mode description below for further detailed requirements.
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
(0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above SGND. For
example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven
by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential
input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.
SGND DC, or it exceeds the maximum input current limitations, then it must be AC-coupled
off-chip.
SerDes Reference Clock Receiver Characteristics
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
Figure
SD n _REF_CLK
SD n _REF_CLK
39. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
Figure 39. Receiver of SerDes Reference Clocks
DD_
50 W
50 W
SRDSn are specified in
Input
Amp
Table 1
Freescale Semiconductor
and
Table
2.