MC8640DTHX1067NE Freescale Semiconductor, MC8640DTHX1067NE Datasheet - Page 70

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MC8640DTHX1067NE

Manufacturer Part Number
MC8640DTHX1067NE
Description
IC MPU DUAL CORE E600 1023FCCBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC8640DTHX1067NE

Processor Type
MPC86xx PowerPC 32-Bit
Speed
1.067GHz
Voltage
0.95V
Mounting Type
Surface Mount
Package / Case
1023-FCCBGA
Processor Series
MPC8xxx
Core
e600
Development Tools By Supplier
MCEVALHPCN-8641D
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No

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Part Number:
MC8640DTHX1067NE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
PCI Express
Maximum time to
transition to a
valid electrical
idle after sending
an electrical idle
ordered set
Maximum time to
transition to valid
Tx specifications
after leaving an
electrical idle
condition
Differential
Return Loss
Common Mode
Return Loss
DC Differential
TX Impedance
Transmitter DC
Impedance
Lane-to-Lane
Output Skew
AC Coupling
Capacitor
Crosslink
Random
Timeout
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in
3. A T
4. The transmitter input impedance shall result in a differential return loss greater than or equal to 12 dB and a common mode
5. Measured between 20–80% at transmitter package pins into a test load as shown in
6. See Section 4.3.1.8 of the PCI Express Base Specifications Rev 1.0a
7. See Section 4.2.6.3 of the PCI Express Base Specifications Rev 1.0a
8. MPC8640D SerDes transmitter does not have C
70
any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in
transmitter collected over any 250 consecutive Tx UIs. The T
TX jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as opposed
to the averaged time value.
return loss greater than or equal to 6 dB over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+ and
D– line (that is, as measured by a Vector Network Analyzer with 50 Ω probes—see
C
Parameter
TX
TX-EYE
is optional for the return loss measurement.
= 0.70 UI provides for a total sum of deterministic and random jitter budget of T
MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3
T
T
TX-IDLE-TO-DIFF-DATA
TX-IDLE-SET-TO-IDLE
Z
Table 49. Differential Transmitter Output Specifications (continued)
RL
L
TX-DIFF-DC
Symbol
RL
T
Z
TX-SKEW
crosslink
TX-DIFF
TX-DC
C
TX-CM
TX
Min
12
80
40
75
6
0
Nom
100
TX
built-in. An external AC coupling capacitor is required.
500 +
Max
2 UI
120
200
20
20
1
TX-EYE-MEDIAN-to-MAX-JITTER
Units
ms
dB
dB
nF
UI
UI
ps
Ω
Ω
After sending an electrical idle ordered set, the
transmitter must meet all electrical idle specifications
within this time. This is considered a debounce time for
the transmitter to meet electrical idle after transitioning
from L0.
Maximum time to meet all Tx specifications when
transitioning from electrical idle to sending differential
data. This is considered a debounce time for the Tx to
meet all Tx specifications after leaving electrical idle
Measured over 50 MHz to 1.25 GHz. See Note 4
Measured over 50 MHz to 1.25 GHz. See Note 4
TX DC differential mode low impedance
Required TX D+ as well as D– DC impedance during
all states
Static skew between any two transmitter lanes within a
single link
All transmitters shall be AC coupled. The AC coupling
is required either within the media or within the
transmitting component itself. See Note 8.
This random timeout helps resolve conflicts in crosslink
configuration by eventually resulting in only one
downstream and one upstream port. See Note 7.
Figure
Figure 52
median is less than half of the total
52). Note that the series capacitors
TX-JITTER-MAX
Figure
Notes
Figure 52
for both V
Freescale Semiconductor
50)
= 0.30 UI for the
TX-D+
and measured over
and V
TX-D–
.

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