PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet
PEF20550HV2.1XT
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PEF20550HV2.1XT Summary of contents
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ICs for Communications Extended Line Card Interface Controller ® ELIC PEB 20550 PEF 20550 Versions 1.3 User’s Manual 01.96 T2055-0V13-M1-7600 ...
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Edition 01.96 This edition was realized using the software system FrameMaker . Published by Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights ...
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PEB 20550 PEF 20550 Revision History: Previous Release: Page (in Page Subjects (major changes since last revision) Previous (in User’s Release) Manual) 13 PEF 20550 (ext. temperature range; new) 38 System Integration and Application (DECT added Boundary scan ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.2.7.4 Protocol Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.8.6.4 PCM- and CFI-Interface Activation Example . . . . . . . . . . . . . . . . . . . . . .117 3.8.6.5 SACCO-B Initialization Example . . . . . ...
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Table of Contents 4.6.28 Status Register EPIC®-1 (STAR_E .155 4.6.29 Command Register EPIC®-1 ...
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Table of Contents 4.8.7 D-Channel Enable Register IOM-Port 3 (DCE3 .189 4.8.8 Transmit D-Channel Address Register (XDC ...
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Table of Contents 5.5.3 Monitor/Feature Control (MF) Handler . . . . . . . . . . . . . . . . . . . . . . . . . .304 5.5.3.1 Registers used in Conjunction with ...
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Table of Contents 6.1.6 Calling up Subscriber ...
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Overview The PEB 20550 (Extended Line Card Controller highly integrated controller circuit optimized for line card and key system applications. It combines all functional blocks necessary to manage digital (ISDN or proprietary ...
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SLIC 16 x t/r r SLIC Figure 1 Example for an Integrated Analog / Digital PBX Semiconductor ...
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Extended Line Card Interface Controller ® ELIC Versions 1.3 1.1 Features Switching (EPIC ® -1) • Non-blocking switch for 32 digital (e.g. ISDN voice subscribers – Bandwidth 16, 32 kbit/s – Two consecutive 64-bit/s channels can ...
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Handling of Layer-1 Functions (EPIC • Change detection for C/I-channel (IOM-configuration) or feature control (SLD-configuration) • Additional last-look logic for feature control (SLD-configuration) • Buffered monitor (IOM-configuration) or signaling channel (SLD-configuration) Handling of Layer-2 Functions (SACCO) • Two independent full ...
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Pin Configuration (top view RxD0 61 TSC0 62 TxD0 63 TSC1 64 TxD1 65 TSC2 66 TxD2 67 TSC3 68 TxD3 69 PFS 70 70 PDC TCK 73 TDO 74 TDI 75 ...
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Pin Definitions and Functions -Processor Interface Pin No. Symbol Input (I) Output (O) 6 CSE I 7 CSS I 8 WR, I R AD0, D0 I/O 13 AD1, D1 I/O 14 AD2, D2 I/O ...
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Pin Definitions and Functions (cont’d) -Processor Interface Pin No. Symbol Input (I) Output (O) 77 P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, P0.7, P1.0 ...
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Pin Definitions and Functions (cont’d) ® EPIC -1 Interface Pin No. Symbol Input (I) Output (O) 70 PFS I 71 PDC I 61 RxD0 I 60 RxD1 I 59 RxD2 I 58 RxD3 I 63 TxD0 O 65 TxD1 O ...
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Pin Definitions and Functions (cont’d) ® EPIC -1 Interface Pin No. Symbol Input (I) Output (O) 29 DU0/SIP4 I/IO (OD) 30 DU1/SIP5 I/IO (OD) 32 DU2/SIP6 I/IO (OD) 33 DU3/SIP7 I/IO (OD) 34 DD0/SIP0 O/IO (OD) 35 DD1/SIP1 O/IO (OD) ...
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Pin Definitions and Functions (cont’d) SACCO-Interface Pin No. Symbol Input (I) Output (O) 49 HFSA I 50 HFSB I 48 HDCA I 52 HDCB I 44 RxDA I 56 RxDB I 46 TxDA O (OD) 54 TxDB O (OD) 47 ...
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Pin Definitions and Functions (cont’d) SACCO-Interface Pin No. Symbol Input (I) Output (O) 42 DRQRA O 40 DRQRB O 43 DRQTA O 41 DRQTB O 39 DACKA I 38 DACKB I Semiconductor Group Function DMA-Request Receiver Channel A/B The receiver ...
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Pin Definitions and Functions (cont’d) Boundary Scan Interface, according to IEEE Std. 1149.1 Pin No. Symbol Input (I) Output (O) 76 TMS I (internal pull-up) 75 TDI I (internal pull-up) 74 TDO O 73 TCK I Note: Pin 75 (TDI) ...
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Logic Symbol Boundary Scan Interface FSC DCL DD CFI DU Port 0 DD CFI Port CFI DU Port 2 DD CFI Port 3 DU HFSB HDCB CxDB HDLC Channel B RxDB TxDB TSCB DRQRB DMA Interface ...
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Functional Block Diagram Serial Interface B Watch Dog Timer Powerup RESEX Reset RESIN Generator TMS Boundary TCK Scan TDI Controller TDO DMA Interface A Interface B Figure 4 Semiconductor Group Serial Interface A SACCO-B SACCO-A Bus Interface Unit DMA ...
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System Integration and Application The main application fields of the ELIC are: – Digital line cards, different architectures are supported, – Central control units of key systems, – Analog line cards, – DECT line cards. 1.6.1 Digital Line Card ...
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R IOM -2 Interface C/I, Monitor Channel µP Figure 5 Data Flow - B-channels, Layer-1 Control, Group Controller Signaling Another possibility to handle the point-to-multi-point configuration between a group controller and several line cards is a bus structure. The collision ...
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D-channel processing is supported by multiple different architectures: 1.6.1.2 Decentralized D-Channel Processing, Multiplexed HDLC-Controller. Typically the D-channel load has a very bursty characteristic. Taking this into account, the ELIC provides the capability to multiplex one HDLC-controller among several subscribers. This ...
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The control channel is unidirectional and forwards the status information of the corresponding D-channel (blocked or available) towards the subscriber terminal. Different existing channel structures are used to implement the control channel between the HDLC-controllers on the line card and ...
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In figure 9 a Control Channel Implementation with OCTAT-P as line card transceiver can be seen. When an additional transceiver device is integrated in the terminal (e. PEB 2081 (SBCX)) the control channel is translated into the A/B-bit ...
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Control Channel Implementation on the S When using the ELIC -interface provides contention resolution as a standard feature. In this structure the 0 QUAT-S modifies the E-bit on the line card, i.e. standard S The control ...
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Decentralized D-Channel Processing, Dedicated HDLC-Controller per Subscriber In this configuration IDECs (ISDN D-channel exchange controller, PEB 2075) handle the layer-2 functions for signaling and data packets in the D-channel. The extracted data is separated and sent via the configuration ...
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D Channel R IOM -2 Interface D Channel µP Figure 12 SACCO-B as Assignable HDLC-Controller R IOM -2 R OCTAT -P R ELIC R IOM -2 R OCTAT -P R IDEC Figure 13 IDEC ® Assignable HDLC-Controller Resources ...
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Central D-Channel Processing In this application the EPIC-1 not only switches the B-channels and performs the C/I- and monitor channel control function, but switches also the D-channel data onto the system highway. In upstream direction the EPIC-1 can combine ...
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Mixed D-Channel Processing, Signaling Decentralized, Packet Data Centralized Another possibility is a mixed architecture with centralized packet data and decentralized signaling handling. This is a very flexible architecture which reduces the dynamic load of central processing units by evaluating ...
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Alternatively, the packet and collision data can be directly exchanged between the IDECs and the PCM-highway. Thus, the full 32 subscriber switching capability of the EPIC-1 is retained. R IOM - p-Data Interface µP Figure 16 Line Card ...
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Key Systems The ELIC is an optimal solution for key systems like a PBX. When selecting the multiplexed D-channel architecture, the ELIC covers switching, layer-1 and layer-2 control for the entire system. Together with the IOM-2 compatible Siemens transceiver ...
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OCTAT - Subscribers OCTAT -P (S adapter 0 optional) OCTAT -P 4 Analog SICOFI -4 Subscribers Figure 19 Key System Architecture, Maximum Size 1.6.3 Analog Line Card Together with the highly flexible Siemens codec filter circuits SLICOFI, ...
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DECT Applications 1.6.4.1 Adaptation of a DECT System to an Existing PBX When adding a DECT system to an existing PBX, the line interface of the DECT system must provide the PBX with PCM-coded voice data. Depending on the ...
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In this configuration the base stations are connected to the line interface of the CCFP via U (OCTAT-P). The 4 bit ADPCM voice channels provided by the base stations are PN switched (by the ELIC) to the PCM - ADPCM ...
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DECT Line Card Design for an Existing PBX Today most of the PBX´s have a modular design, meaning they can be extended by adding an analog or digital line card. This enables a user to integrate a DECT system ...
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Functional Description 2.1 General Functions and Device Architecture The ELIC integrates the existing Siemens device PEB 2055 (EPIC-1), a two channel HDLC-Controller (SACCO: Special Application Communication Controller) with a PEB 2050 (PBC) compatible auto-mode, a D-channel arbiter, a configurable ...
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ALE D 0-7 A 0-7 DS R/W CSS CSE R ELIC with Motorola Type Interface Figure 23 Selectable Bus Interface Structures In order to simplify the use of 8- and 16-bit Siemens / Intel type CPUs, different register addresses are ...
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Watchdog Timer To allow recovery from software or hardware failure, a watchdog timer is provided. After reset the watchdog timer is disabled. When setting bit SWT in the watchdog timer control register WTC it is enabled. The only possibility ...
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RESIN pulse width. The activation of RESEX causes an immediate activation of RESIN. Upon the deactivation of RESEX however, RESIN is deactivated only with the next rising PDC-edge. A PFS-frequency of 8-kHz results in ...
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Boundary Scan Support The ELIC provides fully IEEE Std. 1149.1 compatible boundary scan support consisting of: – a complete boundary scan – a test access port controller (TAP) – four dedicated pins (TCK, TMS, TDI, TDO) – a 32-bit ...
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Table 6 Boundary Scan Sequence (cont’d) Boundary Pin Number Pin Name Scan Number TDI ...
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Table 6 Boundary Scan Sequence (cont’d) Boundary Pin Number Pin Name Scan Number TDI ...
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Table 6 Boundary Scan Sequence (cont’d) Boundary Pin Number Pin Name Scan Number TDI 2.2.5.2 TAP-Controller The Test Access Port (TAP) controller implements the ...
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INTEST supports internal chip testing. When the TAP-controller is in the state "update DR", all inputs are updated internally with the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs are latched with ...
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Configurable Interface In order to optimize the on-board interchip communication, a very flexible serial interface is available. It formats the data transmitted or received at the DDn-, DUn- or SIPn-lines. Although it is typically used in IOM-2 or SLD-configuration ...
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Pre-processed Channels, Layer-1 Support The EPIC-1 supports the monitor/feature control and control/signaling channels according to SLD- or IOM-2 interface protocol. The monitor handler controls the data flow on the monitor/feature control channel either with or without active handshake protocol. ...
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Special Functions – Synchronous transfer. This utility allows the synchronous P-access to two independent channels on the PCM- or CFI-interface. Interrupts are generated to indicate the appropriate access windows. – 7-bit hardware timer. The timer can be used to ...
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The SACCO consists of the following logical blocks: Figure 25 SACCO-Block Diagram (one channel) 2.2.7.2 Parallel Interface All registers and the FIFOs are accessible via the ELIC parallel P-interface. The chip select signal CSS selects the SACCO for read/write access. ...
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Interrupts The SACCO indicates special events by issuing an interrupt request. The cause of a request can be determined by reading the interrupt status register ISTA_A/B or EXIR_A/ B. The related register is flagged in the top level ISTA (refer ...
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Figure 26 Timing Diagram for DMA-Transfers (fast) Transmit (n < 32, remainder of a long message 32) DRQT WR CSS, DACK Cycle Figure 27 Timing Diagram for DMA-Transfers (slow) Transmit (n < 32, remainder of a ...
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Figure 28 Timing Diagram for DMA-Transfer (fast) Receive ( DRQR RD CSS, DACK Cycle Figure 29 Timing Diagram for DMA-Transfers (slow) Receive ( DRQR RD CSS, DACK Cycle Figure 30 Timing Diagram for DMA-Transfers (slow or ...
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For further information refer to chapter 3.6.2 (Data Transmission in DMA-Mode) and chapter 3.6.4 (Data Reception in DMA-Mode). DRQR / DRQT DACK Figure 31 DMA-Transfers with Pulsed DACK (read or write pulsed DACK-signal is used ...
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RME-interrupt is generated. The configuration of the RFIFO prior to and after acknowledgment is shown in figure 32 (left). If frames longer than 64 bytes are received, the SACCO will repeatedly prompt to read out 32-byte data blocks via interrupt ...
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The status of the bit MODE:CFT (continuous frame transmission) defines whether a new frame can be loaded as soon as the XFIFO is available or after the current transmission was terminated. Frame Transmission Transmit Serial Data Copy Data to Inaccessable ...
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If the data transfer is initiated via the proper command, the SACCO automatically requests the correct amount of block data transfers (n by activating the DRQT-line. Refer to chapter 2.2.7.2 for a detailed description of the DMA transfer timing. 2.2.7.4 ...
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Address Recognition Address recognition is performed in three operating modes (auto-mode, non-auto-mode and transparent mode 1). Two pairs of compare registers (RAH1, RAH2: high byte compare, RAL1, RAL2: low byte compare) are provided. RAL2 may be used for a broadcast ...
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Table 8 Address Recognition (cont’d) Operating Compare Mode Value High Byte Non-auto – mode, – 1-byte address field <RAH1> <RAH2> Transparent mode 1 FCH FEH Auto-Mode (MODE:MDS1,MDS0 = 00) Characteristics: HDLC formatted, NRM-type protocol, 1-byte/2-byte address field, address recognition, any ...
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Receive Direction In auto-mode the SACCO provides address recognition for 2- and 1-byte address fields. The auto-mode protocol is only applied when RAL1 respectively RAH1/RAL1 match. With any other matching combination, the frame is transferred transparently into the RFIFO and ...
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I-frames When an I-frame is received in auto-mode the first data byte is interpreted as a command byte according to the PEB 2050 (PBC) protocol. Depending on the value of the command byte one of the following actions is performed. ...
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Transmit Direction, Response Generation In auto-mode frames are only transmitted after the reception of a RR- or I-frame with poll bit set. Table 12 Auto-Mode Response Generation Received Frame Response RR-poll I-frame with XFIFO-data poll bit set RR-response I-frame, first ...
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According to the PBC conventions, the control response byte has the following structure: bit bit7 … bit5 : 1 bit4 : AREP : 1/0: autorepeating is enabled/disabled bit3 … bit1 : ...
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WR XFIFO CMDR : XDD ISTA : XPR WR XFIFO CMDR : XDD/XME ISTA : XPR Figure 36 Polling Bytes Direct Data If more than 64 bytes are transmitted, the XFIFO is used as an intermediate ...
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When the group controller wants the SACCO to re-transmit a frame (e.g. due to a CRC- error) it does not answer with a RR-acknowledge but emits a second RR-poll. The SACCO then generates an XMR-interrupt (transmit message repeat) indicating the ...
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WR XFIFO CMDR : XDD/XME/AREP ISTA : XPR Figure 39 Re-transmission of a Frame with Auto-Repeat Function Polling of Prepared Data If polling "prepared data" a different procedure is used. The group controller issues an I-frame with a set poll ...
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ISTA : RME RD RFIFO SACCO Slave WR XFIFO CMDR : XPD/ XME/AREP ISTA : XPR Figure 40 Polling of Prepared Data Behavior of SACCO when a RFIFO Overflow Occurs in Auto-mode When the RFIFO overflows during the reception of ...
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Depending on the number of bytes to be stored in the RFIFO the following behavior occurs: RFIFO Handling/Steps Receive frame After 32 bytes are received After next 31/32 bytes are received Additional I-poll Additional RR-poll Read and acknowledge RFIFO Read ...
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Non-Auto-Mode (MODE:MDS1, MDS0 = 01) Characteristics: HDLC formatted, 1-byte/2-byte address field, address recognition, any message length, any window size. All frames with valid address fields are stored in the RFIFO and an interrupt (RPF, RME) is issued. The HDLC-control field, ...
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Extended Transparent Mode 0 (MODE:MDS1, MDS0, ADM = 110) Characteristics: fully transparent without HDLC framing, any message length, any window size. Data is stored in register RAL1. In extended transparent mode, fully transparent data transmission/reception without HDLC-framing is performed, i.e. ...
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FLAG ADDRESS RAH 1 RAH MDS 1 MDS 0 ADM Automode/16 RAH 2 or FCH or FEH RAH 1 or RAH 2 or FCH or FEH RAL 1 MDS 1 MDS 0 ADM RAL ...
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Note: RR-frames and I-frame with first data byte equal to Ax processed automatically. They are not stored in RFIFO and no interrupt is issued. 2.2.7.5 Special Functions Cyclical Transmission (fully transparent) When the extended transparent mode is selected, the SACCO ...
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This feature is enabled by setting the RC- (receive check) bit in RLCR and programming the maximum frame length via bits RL6…RL0. According to the value written to RL6…RL0, the maximum receive length can be adjusted in multiples of 32-byte ...
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Together TSN and CS provide 9 bits to determine the location of the time slot for the HDLC channel. One time slots can be programmed independently for receive and transmit direction via the registers TSAR and ...
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Clock Mode 3 In clock mode 3 SACCO-A is multiplexed among multiple subscribers under the control of the D-channel arbiter. It must be used only in combination with transparent mode 0. Serial data is transferred on (received from) the D-channels ...
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Serial Port Configuration The SACCO supports different serial port configuration, enabling the use of the circuit in – point-to-point configurations – point-to-multi-point configurations – multi master configurations Point-to-Point Configuration The SACCO transmits frames without collision detection/resolution. (CCR1:SC1, SC0: 00) ...
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Compared to the Version 1.2 the Version 1.3 provides new features: Push-pull operation may be selected in bus configuration (up to Version 1.2 only open drain): • When active TXDA / TXDB outputs serial data in push-pull-mode. • When inactive ...
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D-Channel Arbiter The D-channel arbiter facilitates the simultaneous serving of multiple D-channels with one HDLC-controller (SACCO-A) allowing a full duplex signaling protocol (e.g. LAPD). It builds the interface between the serial input/output of SACCO-channel A and the time slot ...
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Upstream Direction In upstream direction the arbiter assigns the receive channel of SACCO-A to one subscriber terminal. It uses an unidirectional control channel to indicate the terminals whether their D-channels are available or blocked. The control channel is implemented ...
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When SACCO-A indicates the recognition of a frame (frame indication after receiving 3 bytes incl. the flag) before the suspend counter underflows the ASM enters the state "receive frame". (6) The ASM-state changes from "receive frame" to "limited selection" ...
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SACCO_A : Receiver Reset and Clock Mode = Strobe On * Latch Ch-Address * Restart Suspend Counter * Latch DCES Registers Full Selection * Strobe On * Latch Ch-Address * Restart Suspend Counter R n IOM Frames ...
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Control Channel Master The control channel master (CCM) issues the "D-channel available" information in the control channel as shown in table 13 D-channel is not enabled by the arbiter, the control channel passes the status, stored in the ...
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When a D-channel is enabled in the DCE-register and available, the control channel master takes priority over the C/I- (MR) values stored in the EPIC-1 control memory and writes out either C/I = x0xx. When a ...
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Control Channel Delay Depending on the selected system configuration different delays between the activation of the control channel and the corresponding D-channel response occur. Table 14 Control Channel Delay Examples System Circuit Chain Configuration U line card - ELIC ...
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In order to avoid such a locking situation the time has to be greater then the maximum delay t plus the delay . DCDU For the QUAT-S a value recommended for the suspend counter (register SCV). For ...
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Operational Description The ELIC, designed as a flexible line-card controller, has the following main applications: – Digital line cards, with the CFI typically configured as IOM-2, IOM-1 (MUX) or SLD. – Analog line cards, with the CFI typically configured ...
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When using the Siemens / Intel multiplexed interface, the ELIC can be addressed – either with even addresses only (i.e. AD0 always 0), which allows data always to be transferred in the low data byte, – or with even and ...
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When serving an ELIC-interrupt, the user first reads the top level interrupt status register (ISTA). This register flags which subblock has generated the request subblock can issue different interrupt types a local ISTA/EXIR exists. A read of the ...
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Reset After power-up the ELIC is locked in the "resetting" state. Neither read not write accesses are possible while the ELIC is resetting. There are two ways to release the ELIC into the operational/programmable state: a) With an active ...
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PCM-back plane. Due to its capability to dynamically switch the 16-kbit/s D-channel, the EPIC-1 is one of the fundamental building blocks for networks with either central, decentral or mixed signaling and packet data handling architecture. 3.5.1 PCM-Interface The ...
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The actual position of the external upstream and downstream PCM-frames with respect to the framing signal PFS can still be adjusted using the PCM-offset function of the EPIC-1. The offset can then be programmed such that PFS marks any bit ...
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The CFI-standby function switches all CFI-output lines to high impedance with a single command. Internally the device still works normally, only the output drivers are switched off. The number of time slots per 8-kHz frame is programmable from 2 to ...
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Figure 47 Switching Paths Inside the EPIC Note that the time slot selections in upstream direction are completely independent of the time slot selections in downstream direction. CFI - PCM Time Slot Assignment Switching paths 1 and 2 of figure ...
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Sub Time Slot Switching Sub time slot positions at the PCM-interface can be selected at random, i.e. each single PCM time slot-may contain any mixture of 2- and 4-bit sub time slots. A PCM time slot may also contain more ...
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Even Control Memory Address MAAR = 0......0 DD Application Code Field Data Field MACR = 0111... MADR = ...... Decentral D Channel Handling Central D Channel Handling 6 ...
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Synchronous Transfer For two channels, all switching paths of figure 47 can also be realized using Synchronous Transfer. The working principle is that the P specifies an input time slot (source) and an output time slot (destination). Both source and ...
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If transparent or direct data is sent, CMDR:XME may but need not be set. If CMDR:XME is not set, the SACCO will repeatedly request for the next data block by means of a XPR-interrupt as ...
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Serial Interface SACCO CPU Interface WR XTF 32 Bytes Figure 50 Interrupt Driven Transmission Sequence Example 3.6.2 Data Transmission in DMA-Mode Prior to data transmission, the length of the frame to be transmitted must be programmed via the Transmit ...
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Data Reception in Interrupt Mode In receive direction 2 32-byte FIFO-buffers (receive pools) are also provided for each channel. There are two different interrupt indications concerned with the reception of data: – A RPF (Receive Pool Full) interrupt indicates ...
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Data Reception in DMA-Mode If the RFIFO contains 32 bytes, the SACCO autonomously requests a block DMA- transfer by activating the DRQR-line. This forces the DMA-controller to continuously perform bus cycles until 32 bytes are transferred from the SACCO ...
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D-Channel Arbiter The D-channel arbiter links the SACCO-A to the CFI of the EPIC-1. EPIC-1 and SACCO-A should therefore be initialized before setting up the D-channel arbiter, as demonstrated in chapter 3.8. In downstream direction, the D-channel arbiter distributes ...
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SACCO-A Reception Subscribers who are to participate in the D-channel arbitration for the SACCO-A must send ’all 1s’ as inter frame timefill of their D-channels. Flags or idle codes other than ’all 1s’ are not permitted as inter frame ...
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Initialization Procedure For proper initialization of the ELIC the following procedure is recommended: 3.8.1 Hardware Reset A reset pulse can be applied at the RESEX-pin for at least 4 PDC-clock cycles. The reset pulse sets all registers to their ...
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The resetting of the complete CM takes 256 RCL-clock cycles. During this time, the EPIC.STAR:MAC-bit is set to logical 1. 3.8.2.3 Initialization of Pre-processed Channels After the CM-reset, all CFI time slots are unassigned. If the CFI is used as ...
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Example In CFI-mode 0 all four CFI-ports shall be initialized as IOM-2 ports with a 4-bit C/I-field and D-channel handling by the SACCO-A. CFI time slots initialized. CFI time slots ...
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Initialization of the Upstream Data Memory (DM) Tristate Field For each PCM time slot the tristate field defines whether the contents of the DM-data field are to be transmitted (low impedance), or whether the PCM time slot shall be ...
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Table 17 Mode Dependent Register Set-up Transparent mode 1 Non-auto mode Auto-mode The second minimum register to be initialized is the CCR2. In combination with the CCR1, the CCR2 defines the configuration of the serial port. It also allows enabling ...
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Switching between power-up or power-down mode has no effect on the contents of the register, i.e. the internal state remains stored. After power-up of the SACCO, the CPU should bring the transmitter and receiver to a defined state by issuing ...
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Note: The EPIC-1 and SACCO-A must be initialized correctly before the D-channel arbiter can operate properly. Particular care must be given to programming the EPIC-1’s Control Memory (CM) with the required CM-Codes (CMCs). Note: The upstream and downstream D-channel arbiter ...
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Initialization Example In this sample initialization the ELIC is set up to handle a digital IOM-2 subscriber. The interfaces of the ELIC are shown below: R IOM -2 Interface µP Figure 54 ELIC ® Interfaces for Initialization Example The ...
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EPIC ® -1 Initialization Example Configure PCM-side of ELIC: Write PMOD = 44 H Write PBNR = FF H Write POFD = F0 H Write POFU = 18 H Write PCSR = 45 H Configure CFI-side of ELIC: Write ...
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The subscriber’s upstream time slots 2 and 3 are initialized as monitor and C/I-channels with decentral D-channel handling Write MADR = FF H Write MAAR = 88 H Write MACR = 78 H Read STAR Write MAAR = 89 H ...
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Set EPIC-1 to normal mode Write OMDR = C0 H Read ISTA = 20 H Read ISTA_E = 08 H Read STAR_E = 25 H Reset tristate field of Data Memory (DM) Write MADR = 00 H Write MACR = ...
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PCM- and CFI-Interface Activation Example Write OMDR = EE H Enable upstream PCM-port 0, time slot 5 Write MADR = 0F H Write MAAR = 89 H Write MACR = 60 H Read STAR 3.8.6.5 SACCO-B Initialization Example Configure ...
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Detailed Register Description 4.1 Register Address Arrangement Interrupt Top Level Group Reg Chip Name Select Interrupt ISTA CSE top level MASK CSE Parallel Ports Group Reg Chip Name Select PORT0 PORT0 CSE PORT1 PORT1 CSE PCON1 CSE Watchdog Timer ...
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EPIC ® -1 Group Reg Chip Name Select PMOD CSE PBNR CSE POFD CSE EPIC-1- PCM POFU CSE interface PCSR CSE PICM CSE CMD1 CSE CMD2 CSE CBNR CSE EPIC-1 CTAR CSE CFI CBSR CSE CSCR CSE MACR CSE EPIC-1 ...
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EPIC ® -1 (cont’d) Group Reg Chip Name Select STDA CSE STDB CSE SARA CSE EPIC-1 SARB CSE synchro- nous transfer SAXA CSE SAXB CSE STCR CSE MFAIR CSE EPIC-1 monitor/ MFSAR CSE feature control MFFIFO CSE CIFIFO CSE TIMR ...
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SACCO Group Reg Chip Name Select RFIFO CSS SACCO- FIFO XFIFO CSS ISTA_A/B CSS MASK_A/B CSS EXIR_A/B CSS CMDR CSS MODE CSS SACCO- CCR1 CSS status/ control CCR2 CSS RLCR CSS STAR CSS RSTA CSS RHCR CSS SACCO- XAD1 CSS ...
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SACCO (cont’d) Group Reg Chip Name Select RBCL CSS RBCH CSS SACCO- DMA- XBCL CSS support XBCH CSS TSAX CSS TSAR CSS SACCO- time slot assignment XCCR CSS RCCR CSS SACCO VSTR CSS version Semiconductor Group Access Address Address mux ...
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Arbiter Group Reg Chip Name Select AMO CSE Arbiter ASTATE CSE control SCV CSE DCE0 CSE DCE1 CSE D-Channel enabling DCE2 CSE upstream DCE3 CSE XDC CSE BCG0 CSE D-Channel BCG1 CSE selecting downstream BCG2 CSE BCG3 CSE Semiconductor Group ...
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Interrupt Top Level 4.2.1 Interrupt Status Register (ISTA) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 IWD IDA IWD Interrupt Watchdog Timer. The watchdog timer is expired and an external reset ...
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Mask Register (MASK) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value: 00 (all interrupts enabled) H bit 7 0 IDA IDA enables(0)/disables(1) the D-Channel Arbiter interrupt IEP enables(0)/disables(1) the EPIC-1 Interrupts EXB enables(0)/disables(1) the SACCO-B ...
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Parallel Ports 4.3.1 PORT0 Data Register (PORT0) Demultiplexed address mode: Access in multiplexed P-interface mode: Reset value bit 7 P0D7 P0D6 P0D5 P0D7..0 PORT0 data 7…0. Data sampled on the related pin with the falling RD-edge. Note: ...
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Port1 Configuration Register (PCON1) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit P1C3..0 PORT1 Configuration 3…0. 0…port1, pin # is configured as input. 1…port1, pin # is configured as ...
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ELIC ® Mode Register / Version Number Register (EMOD) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 VN3 VN2 VN(3:0) ELIC-Version Number according to the following table: VN (3:0) 1111 1110 ...
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PCSR:DRE has to be set to ‘1’. PCSR:URE has to be set to ‘1’. When provided with a 2 MHz PDC, the ELIC internally generates a 4 MHz clock. Since the clock shift capabilities (provided by register bits PCSR:DRCS ...
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EPIC ® -1 4.6.1 PCM-Mode Register (PMOD) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 PMD1 PMD0 Note: If EMOD:ECMD2 is set to ’0’ some restrictions apply to the setting of ...
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AIS1..0 Alternative Input Selection. These bits determine the relationship between the physical pins and the logical port numbers. The logical port numbers are used when programming the switching functions. Note: In PCM-mode 0 these bits may not be set! PCM ...
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Bit Number per PCM-Frame (PBNR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 BNF7 BNF6 BNF5 BNF7..0 Bit Number per PCM Frame. PCM-mode 0: BNF7..0 = number of bits – 1 ...
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PCM-Offset Upstream Register (POFU) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 OFU9 OFU8 OFU7 OFU9..2 Offset Upstream bit 9…2. These bits together with PCSR:OFU1..0 determine the offset of the PCM- ...
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PCM-Clock Shift Register (PCSR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 DRCS OFD1 OFD0 DRCS Double Rate Clock Shift. 0…the PCM-input and output data are not delayed 1…the PCM-input and ...
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PCM-Input Comparison Mismatch (PICM) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 IPN TSN6 TSN5 IPN Input Pair Number. This bit denotes the pair of ports, where a bit mismatch occurred. ...
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Configurable Interface Mode Register 1 (CMD1) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 CSS CSM CSP1 CSS Clock Source Selection. 0…PDC and PFS are used as clock and framing source ...
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CMD1..0 CFI-Mode1,0. Defines the actual number and configuration of the CFI-ports. CMD1..0 CFI- Mode CFI-mode 0 data rate of 2.048 kBit/s can be used with a 2.048-kBit/s PDC-input clock, if ...
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Configurable Interface Mode Register 2 (CMD2) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 FC2 FC1 FC2..0 Framing output Control. Given that CMD1:CSS = 0, these bits determine the position of ...
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CFI Last Time-Slot of a Frame Frame RCL DCL DCL DCL FSC FSC FSC FSC FSC Figure 56 Position of the FSC-Signal for FC-Modes and 6 Time-Slot CFI 0 1 Frame FSC FSC RCL Figure 57 ...
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Application examples: FC2 FC1 FC0 For further details on the framing output control please refer to ...
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Configurable Interface Bit Number Register (CBNR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 CBN7 CBN6 CBN5 CBN7..0 CFI-Bit Number 7..0. The number of bits that constitute a CFI-frame must be ...
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Configurable Interface Bit Shift Register (CBSR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 0 CDS2 CDS1 CDS2..0 CFI-Downstream bit Shift 2..0. From the zero offset bit position (CBSR = 20 ...
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Configurable Interface Subchannel Register (CSCR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 SC31 SC30 SC21 SC#1..#0 CFI-Subchannel Control for logical port #. The subchannel control bits SC#1..SC#0 specify separately for ...
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Memory Access Control Register (MACR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RWS MOC3 MOC2 With the MACR the P selects the type of memory (CM or DM), the type ...
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Note: When reading a DM-data field location, all 8 bits are read regardless of the bandwidth selected by the MOC-bits. 2. Writing to the upstream DM-code (tristate) field. Control-reading the upstream DM-code (tristate). MACR: RWS MOC3 MOC2 MOC = 1100 ...
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Pre-processed Applications Downstream: Application Decentral D-channel handling Central D-channel handling 6-bit Signaling (e.g. analog IOM) 8-bit Signaling (e.g. SLD) D-Channel handling by SACCO-A with ELIC-arbiter Upstream: Application Decentral D-channel handling Central D-channel handling 6-bit Signaling (e.g. analog IOM) 8-bit ...
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Memory Access Address Register (MAAR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 U/D MA6 The Memory Access Address Register MAAR specifies the address of the memory access. This address encodes ...
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Table 20 Time Slot Encoding for Control Memory Accesses CFI-mode 0 CFI-mode 1 CFI-mode 2 CFI-mode 3 4.6.15 Memory Access Data Register (MADR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MD7 ...
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Synchronous Transfer Data Register B (STDB) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MTDB7 MTDB6 MTDB5 The STDA-register buffers the data transferred over the synchronous transfer channel A. MTDA7 to ...
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Synchronous Transfer Receive Address Register B (SARB) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 ISRB MTRB6 MTRB5 The SARB-register specifies for synchronous transfer channel B from which input interface, port ...
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Synchronous Transfer Transmit Address Register B (SAXB) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 ISXB MTXB6 MTXB5 The SAXB-register specifies for synchronous transfer channel B to which output interface, port ...
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CTB2..0 Note that if a CFI time slot is selected as receive or transmit time slot of the synchronous transfer, the 64-kBit/s bandwidth must be selected (CT#2..CT#0 = 001). CT#2 CT ...
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MF-Channel Subscriber Address Register (MFSAR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MFTC1 MFTC0 SAD5 The exchange of monitor data normally takes place with only one subscriber circuit at a ...
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Signaling FIFO (CIFIFO) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value: 0xxxxxxx B bit 7 SBV SAD6 SAD5 The 9 byte deep CIFIFO stores the addresses of CFI time slots in which a C/I- and/or ...
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TVAL6..0 Timer Value bits 6..0; the timer period, equal to (1+TVAL6..0) programmed here. It can thus be adjusted within the range of 250 ms. The timer is started as soon as CMDR:ST is set to 1 ...
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MFRW MFFIFO Read/Write. 0… the MFFIFO is ready to be written to. 1… the MFFIFO may be read. MFFE MFFIFO Empty 0… the MFFIFO is not empty. 1… the MFFIFO is empty. 4.6.29 Command Register EPIC Access in demultiplexed P-interface ...
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EPIC-1 starts to search for active MF-channels. Active channels are characterized by an active MX-bit (logical 0) sent by the remote transmitter. If such a channel is found, the corresponding address is stored in MFAIR ...
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Interrupt Status Register EPIC Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 TIN SFI The ISTA-register should be read after an interrupt in order to determine the interrupt source. TIN Timer ...
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SIN Synchronous transfer Interrupt; The SIN-interrupt is enabled if at least one synchronous transfer channel (A and/ enabled via the STCR:TAE, TBE-bits. The SIN-interrupt is generated when the access window for the P opens. After the occurrence of ...
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Operation Mode Register (OMDR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 OMS1 OMS0 OMS1..01 Operational Mode Selection; these bits determine the operation mode of the EPIC-1 is working in according ...
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PSB PCM-Standby. 0…the PCM-interface output pins TxD0..3 are set to high impedance and those TSC-pins that are actually used as tristate control signals are set to logical 1 (inactive). 1…the PCM-output pins transmit the contents of the upstream data memory ...
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Version Number Status Register (VNSR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit The VNSR-register bits do not generate interrupts and are not modified by reading VNSR. The IR ...
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SACCO 4.7.1 Receive FIFO (RFIFO) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RD7 RD6 RD7..0 Receive Data 7…0, data byte received on the serial interface. Interrupt controlled data transfer (interrupt ...
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Additionally an RME-interrupt is issued after the last byte has been transferred result, the DMA-controller may transfer more bytes as actually valid in the current received frame. The valid byte count must therefore be determined reading the registers ...
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Interrupt Status Register (ISTA_A/B) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RME RPF RME Receive Message End. A message bytes or the last part of a ...
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Mask Register (MASK_A/B) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value: 00 (all interrupts enabled) H bit 7 RME RPF RME enables(0)/disables(1) the Receive Message End interrupt. RPF enables(0)/disables(1) the Receive Pool Full interrupts. XPR ...
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XMR Transmit Message Repeat. The transmission of a frame has to be repeated because: – A frame consisting of more then 32 bytes is polled a second time in auto- mode. – Collision has occurred after sending the 32nd data ...
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Command Register (CMDR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RMC RHR AREP/ XREP Note: The maximum time between writing to the CMDR-register and the execution of the command is ...
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XPD/XTF Transmit Prepared Data/Transmit Transparent Frame. Auto-mode: XPD Prepares the transmission of an I-frame ("prepared data") in auto-mode. The actual transmission starts, when the SACCO receives an I-frame with poll-bit set and AxH as the first data byte (PBC-command "transmit ...
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Mode Register (MODE) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 MDS1 MDS0 MDS1..0 Mode Select. The operating mode of the HDLC-controller is selected. 00…auto-mode 01…non-auto-mode 10…transparent mode (D-channel arbiter) 11…extended ...
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RAC Receiver Active. Via RAC the HDLC-receiver can be activated/deactivated. 0…HDLC-receiver inactive 1…HDLC-receiver active In extended transparent mode 0 and 1 RAC must be reset (HDLC-receiver disabled) to enable fully transparent reception. TLP Test Loop. When set input and output ...
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Up to Version 1.2 when selecting a bus configuration only the open drain option must be selected. Compared to the Version 1.2 the Version 1.3 provides new features: Push-pull operation may be selected in bus configuration (up to Version 1.2 ...
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Channel Configuration Register 2 (CCR2) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 SOC1 SOC0 XCS0 SOC1, The function of the TSCA/B-pin can be defined programming SOC1,SOC0. SOC0 Bus configuration: 00…the ...
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Receive Length Check Register (RLCR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value: 0xxxxxxx H bit 7 RC RL6 RC Receive Check enable. A ’1’ enables, a ’0’ disables the receive frame length feature. RL6..0 ...
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Status Register (STAR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 XDOV XFW AREP/ XREP XDOV Transmit Data Overflow. A ’1’ indicates, that more than 32 bytes have been written into ...
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Receive Status Register (RSTA) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 VFR RDO RSTA always displays the momentary state of the receiver. Because this state can differ from the last ...
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HA1..0 High byte Address compare. In operating modes which provide high byte address recognition, the SACCO compares the high byte of a 2-byte address with the contents of two individual programmable registers (RAH1, RAH2) and the fixed values FEH and ...
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Receive HDLC-Control Register (RHCR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RHCR7 RHCR6 RHCR5 RHCR7..0 Receive HDLC-Control Register. The contents of the RHCR depends on the selected operating mode. Auto-mode ...
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Transmit Address Byte 2 (XAD2) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 XAD27 XAD26 XAD25 XAD27..20 Transmit Address byte 2. The value stored in XAD2 is included automatically as the ...
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Receive Address Byte Low Register 2 (RAL2) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RAL27 RAL26 RAL25 RAL27..20 Receive Address byte Low register 1. Auto-mode, non-auto mode (address recognition): compare ...
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Receive Address Byte High Register 2 (RAH2) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RAH27 RAH26 RAH25 RAL27..22 Receiver Address byte High register 2. Auto-mode, non-auto mode transparent mode 1, ...
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Receive Byte Count High (RBCH) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value: 000xxxxx H bit 7 DMA 0 DMA DMA-mode status indication. Read back value representing the DMA-bit programmed in register XBCH. OV Counter ...
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Transmit Byte Count High (XBCH) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value: 0000xxxx bit 7 DMA 0 DMA DMA-mode. Selects the data transfer mode between the SACCO FIFOs and the system memory: 0…interrupt controlled ...
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Time Slot Assignment Register Receive (TSAR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 TSNR5 TSNR4 TSNR3 TSNR5..0 Time Slot Number Receive. Selects one time slots (00 ...
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Receive Channel Capacity Register (RCCR) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 RBC7 RBC6 RBC5 RBC7..0 Receive Bit Count. Defines the number of bits to be received in a time ...
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D-Channel Arbiter 4.8.1 Arbiter Mode Register (AMO) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 FCC4 FCC3 FCC2 FCC4..0 Full selection Counter. The value (FCC4.. defines the number of ...
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Arbiter State Register (ASTATE) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 AS2 AS1 AS2..0 Arbiter (receive channel selector) State: 000 : suspended 100 : full selection 011 : limited selection ...
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D-Channel Enable Register IOM-Port 0 (DCE0) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 DCE07 DCE06 DCE05 4.8.5 D-Channel Enable Register IOM-Port 1 (DCE1) Access in demultiplexed P-interface mode: Access in ...
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D-Channel Enable Register IOM-Port 3 (DCE3) Access in demultiplexed P-interface mode: Access in multiplexed P-interface mode: Reset value bit 7 DCE37 DCE36 DCE35 DCEn7..0 D-Channel Enable bits channel 7-0, IOM-port n. 0…D-channel i on IOM-port n is ...
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Broadcast Group IOM-port 0 (BCG0) Access in demultiplexed P-interface mode: Access in multiplexed mP-interface mode: Reset value bit 7 BCE07 BCE06 BCE05 4.8.10 Broadcast Group IOM-port 1 (BCG1) Access in demultiplexed P-interface mode: Access in multiplexed P-interface ...
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Application Hints 5.1 Introduction 5.1.1 IOM ® and SLD Functions IOM ® (ISDN Oriented Modular) Interface The IOM-2 standard defines an industry standard serial bus for interconnecting telecommunications ICs. The standard covers line card, NT1, and terminal architectures for ...
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Frames are delimited kHz frame synchronization signal (FSC). The bit timing and FSC position is identical to the non-multiplexed IOM-1 case. The line card version of the IOM transceivers (ISDN) or codecs (analog), and the line ...
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The terminal version of the IOM ISDN terminal and NT1 applications. It consists of three IOM channels, each containing four 8 bit timeslots. The resultant data transfer rate is therefore 768 kBit/s and the data is clocked with a 1536 ...
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SLD (Subscriber Line Data) Interface The SLD bus is used by the ELIC to interface with the subscriber line devices. A Serial Interface Port (SIP) is used for the transfer of all digital voice and data, feature control and signaling ...
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In contrast to other Siemens telecom devices, the ELIC does not provide an ‘IOM mode’ ‘SLD mode’ that can be selected by programming a single ‘mode bit’. Instead, the ELIC provides a configurable interface (CFI) that can be ...
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The Monitor/Feature Control handler can be adjusted to operate according to the – IOM-1 protocol ( byte, no handshake), the – IOM-2 protocol (any number of bytes, handshake using the MR and MX bits) and to the – ...
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In downstream direction, the P can write the bit C/I or Signaling value to be transmitted directly to the CFI timeslot i.e. to the control memory. This value will then be transmitted repeatedly in each frame ...
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Configuration of Interfaces 5.2.1 PCM Interface Configuration 5.2.1.1 PCM Interface Signals The PCM interface signals are summarized in table 23. Table 23 Signals at the PCM Interface Pin No. Symbol 63 TxD0 65 TxD1 67 TxD2 69 TxD3 62 ...
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PCM Bit Number Register bit 7 PBNR BNF7 BNF6 PCM Offset Downstream Register bit 7 POFD OFD9 OFD8 PCM Offset Upstream Register bit 7 POFU OFU9 OFU8 PCM Clock Shift Register bit 7 PCSR DRCS OFD1 Operation Mode Register bit ...
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ELIC is constant (128 channels per direction), the PCM mode also influences the maximum possible data rate. In each PCM mode a minimum data rate as well as a minimum data rate stepping are specified. ...