PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 226
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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Figure 76
Circuit for Delaying the Framing Signal at the CFI Interface
Semiconductor Group
SYNC
CLK
DIN
DOUT
CLK
SYNC
DOUT
DIN
FSC
additional hardware must delay the frame signal to enable a synchronization with
the positive edge of DCL. Figure 76 gives a suggestion of how to adapt the
external timing.
+5 V
1st Bit
J
PR
CLR
K
1st Bit
Rising FSC edge marks 2nd Bit of frame
J-K Flip-Flop e.g. 74HC112
Q
Q
2nd Bit
2nd Bit
+5 V
226
3rd Bit
J
PR
CLR
K
3rd Bit
Q
Q
4th Bit
4th Bit
Application Hints
FSC
DCL
(DU#)
(DD#)
5th Bit
EPIC
PEB 20550
PEF 20550
5th Bit
R
ITS08055
01.96
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