PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 111

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

be written as MADR = '11xxxx01'
'x' stand for the C/I-code. This also is shown in figure 48.
If the C/I-code is used to block downstream subscribers, such subscribers must be
activated with the C/I-code '1100'
The SACCO-A must be initialized to clock mode 3 to communicate with downstream
subscribers. In clock mode 3, the SACCO-A receives its input and transmit its output via
the D-channel arbiter. If the CCR2.T DE-bit is set, the SACCO-A’s output is transmitted
at the T DA-pin in addition to being transmitted via the D-channel arbiter.
Once EPIC-1 and SACCO-A have been correctly initialized, writing the subscriber’s
address into the XDC-register allows the SACCO-A to send the subscriber data. By
setting the XDC.BCT-bit and programming the BCG-registers, the SACCO-A can
transmit its data to several subscribers.
To strobe upstream data from the CFI-interface to the SACCO-A’s receiver, the AMO-
register must be programmed for the desired functionality. Subscribers who are to be
allowed to send data must be enabled via the DCE-registers. If a subscriber tries to send
data during the initialization of the upstream D-channel arbiter, a ISTA.IDA-interrupt may
occur. This interrupt can be cleared by resetting the SACCO-A receiver.
Switching between power-up or power-down mode has no effect on the contents of the
register, i.e. the internal state remains stored.
After power-up of the SACCO, the CPU should bring the transmitter and receiver to a
defined state by issuing a XRES (transmitter reset) and RHR (receiver reset) command
via the CMDR-register. The SACCO will then be ready to transmit and receive data.
The CPU controls the data transfer phase mainly by commands to the SACCO via the
CMDR-register, and by interrupt indications from the SACCO to the CPU. Status
information that does not trigger an interrupt is constantly available in the STAR-register.
3.8.4
The D-channel arbiter links the SACCO-A to the CFI of the EPIC-1 part of the ELIC. Thus
the EPIC-1 and SACCO-parts of the ELIC should be initialized before initializing the
D-channel arbiter.
For subscribers wishing to communicate with the SACCO-A, the correct pre-processed
channel code must have been programmed in the EPIC-1’s control memory. In
downstream direction, this code is CMC = 1010 for the even time slot and CMC = 1011
for the odd time slot. In upstream direction, any pre-processed channel code is also valid
for arbiter operation. This is shown in figure 48 of chapter 3.5.3. For an example refer
to chapter 3.8.2.3.
If the MR-bit is used to block downstream subscribers, the blocking code MR = '0'
Semiconductor Group
Initialization of D-Channel Arbiter
B
B
, not '1000'
when initializing the even downstream time slot. The
111
B
.
Operational Description
PEB 20550
PEF 20550
B
01.96
can