PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 43

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Activity
1.
2.
they are high during reset, thus containing the correct tristate information for external
drivers.
RESIN is set upon power up, RESEX and the expiring of the watchdog timer. It may be
used as a system reset. RESIN is activated for 8 PFS-periods (assuming an active PDC-
input) or it has the same pulse width as RESEX. RESEX has priority over internal
2.2.3
To allow recovery from software or hardware failure, a watchdog timer is provided.
After reset the watchdog timer is disabled. When setting bit SWT in the watchdog timer
control register WTC it is enabled. The only possibility to disable the watchdog timer is
a ELIC-reset (power-up or RESEX).The timer period is 1024 PFS-cycles assuming that
also PDC is active, i.e. a PFS of 8-kHz results in a timer period of 128 ms.
During that period, the bits WTC1 and WTC2 in the register WTC have to be written in
the following sequence:
Table 2
Watchdog Timer Programming
The minimum required interval between the two write accesses is 2 PDC-periods.
When the software fails to follow these requirements, a timer overflow occurs and a IWD-
interrupt is generated. Additionally an external reset indication (RESIN) is activated. The
internal ELIC-status is not changed.
2.2.4
After power-up the ELIC is latched into the "Resetting" state. A microprocessor access
is not possible in the "Resetting" state. The ELIC is released from the power-up
"Resetting" state when provided with PFS- and PDC-signals for 8 PFS-periods.
The ELIC can also be reset by applying a RESEX-pulse for at least 4 PDC-periods. Note
that such an external RESEX has priority over a power-on reset. It is thus possible to kill
the 8-frame reset duration after power-up.
Upon activation of the power supply an integrated power-up reset generator is provided.
It is generated when
reset input (RESEX) and an reset indication output (RESIN) are available.
During reset all ELIC-outputs with the exception of RESIN and TDO + DRQRA/B +
DRQTA/B + SACCO are in the state high impedance. The tristate control signals of the
EPIC-1 PCM-interface (TSC[3:0]) TSCA/B are not tristated during a chip reset. Instead
Semiconductor Group
Watchdog Timer
Reset Logic
V
DD
is in the range between 1 V and 3 V. Additionally an external
WTC:WTC1
1
0
43
WTC:WTC2
0
1
Functional Description
PEB 20550
PEF 20550
01.96