PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 327

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

Synchronous Transfer Receive
Address Register B
SARB:
The SARB register specifies for synchronous transfer channel B from which input
interface, port, and timeslot the serial data is extracted. This data can then be read from
the STDB register.
ISRB:
MTRB6 … 0:
Synchronous Transfer Receive
Address Register A
SAXA:
The SAXA register specifies for synchronous transfer channel A to which output
interface, port, and timeslot the serial data contained in the STDA register is sent.
ISXA:
MTXA6 … 0:
Synchronous Transfer Transmit
Address Register B
SAXB:
Semiconductor Group
bit 7
bit 7
bit 7
ISRB
ISXA
ISXB
Interface Select Receive for channel B; selects the PCM interface
(ISRB = 0) or the CFI (ISRB = 1) as the input interface for
synchronous channel B.
timeslot number at the interface selected by ISRB according to
figure 84: MTRB6 … 0 = MA6 … 0.
Interface Select Transmit for channel A; selects the PCM interface
(ISXA = 0) or the CFI (ISXA = 1) as the output interface for
synchronous channel A.
timeslot number at the interface selected by ISXA according to
figure 84: MTXA6 … 0 = MA6 … 0.
P Transfer Receive Address for channel B; selects the port and
P Transfer Transmit Address for channel A; selects the port and
MTRB6 MTRB5 MTRB4 MTRB3 MTRB2 MTRB1 MTRB0
MTXA6 MTXA5 MTXA4 MTXA3 MTXA2 MTXA1 MTXA0
MTXB6 MTXB5 MTXB4 MTXB3 MTXB2 MTXB1 MTXB0
327
read/write reset value:
read/write reset value:
read/write reset value:
Application Hints
undefined
undefined
undefined
PEB 20550
PEF 20550
bit 0
bit 0
bit 0
01.96