PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 30

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

When using the ELIC on a S
S
QUAT-S modifies the E-bit on the line card, i.e. standard S
Even with a multiplexed HDLC controller signaling and packet data can be mixed on a
S
data is not delayed by data packets.
Control Channel Implementation on the S
The control channel on the line card is included in the C/I-channel.
Figure 10
Control Channel Implementation on a S
Semiconductor Group
0
0
-interface provides contention resolution as a standard feature. In this structure the
line card. The priority scheme of the S
S
S
0
0
S Phone
S Phone
0
0
S Phone
S Phone
0
0
0
-line card the structure is much simpler because the
0
bus (2 priority classes) guarantees, that signal
0
30
-Line Card
E
E
0
-Interface
QUAT -S
C/I = 1100
C/I = 1000
R
0
-phones can be connected.
C/I
Blocked
Available
ELIC
R
ITS05811
PEB 20550
PEF 20550
Overview
01.96