PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 91

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

active. However, for the duration of a write access to the MASK-register the INT-line is
deactivated. When using an edge-triggered interrupt controller, it is thus recommended
to rewrite the MASK-register at the end of any interrupt service routine.
Masking Interrupts
The watchdog timer interrupt can not be masked. Setting the MASK.IDA-bit masks the
ISTA.IDA-interrupt: a D-channel arbiter interrupt will then neither activate the INT-line
nor be indicated in the ISTA-register. Setting the MASK.IEP/EXB/ICB/EXA or ICA-bits
only masks the INT-line; that is, with a set top level MASK bit these EPIC-1 and SACCO
interrupts are indicated in the ISTA-register but they will not activate the INT-line.
For the ISTA_E, ISTA_A and ISTA_B registers local masking is also provided. Every
interrupt source indicated in these registers can be selectively masked by setting the
respective bit of the local MASK-register. Such locally masked interrupts will not be
indicated in the local or the top ISTA-register, nor will they activate the INT-line.
Locally masked interrupts are internally stored. Thus, resetting the local mask will
release the interrupt to be indicated in the local interrupt register, flagged in the top level
ISTA-register, and to activate the INT-line.
3.3
To operate properly, the ELIC always requires a PDC-clock.
To synchronize the PCM-side, the ELIC should normally also be provided with a PFS-
strobe. In most applications, the DCL and FSC will be output signals of the ELIC, derived
from the PDC via prescalers.
If the required CFI-data rate cannot be derived from the PDC, DCL and FSC can also be
programmed as input signals. This is achieved by setting the EPIC-1 CMD1:CSS-bit.
Frequency and phase of DCL and FSC may then be chosen almost independently of the
frequency and phase of PDC and PFS. However, the CFI-clock source must still be
synchronous to the PCM-interface clock source; i.e. the clock source for the CFI-
interface and the clock source for the PCM-interface must be derived from the same
master clock.
Chapter 5.2.2 provides further details on clocking.
When serving an ELIC-interrupt, the user first reads the top level interrupt status register
(ISTA). This register flags which subblock has generated the request. If a subblock can
issue different interrupt types a local ISTA/EXIR exists.
A read of the top level ISTA-register resets bits IWD and IDA. The other bits are reset
when reading the corresponding local ISTA- or EXIR-registers.
The INT-output is level active. It stays active until all interrupt sources have been
serviced. If a new status bit is set while an interrupt is being serviced, the INT stays
Semiconductor Group
Clocking
91
Operational Description
PEB 20550
PEF 20550
01.96