PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 20

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

47
53
45
55
Pin Definitions and Functions (cont’d)
SACCO-Interface
Pin No.
49
50
48
52
44
56
46
54
Semiconductor Group
Symbol
HFSA
HFSB
HDCA
HDCB
RxDA
RxDB
TxDA
TxDB
TSCA
TSCB
CxDA
CxDB
Input (I)
Output (O)
I
I
I
I
I
I
O (OD)
O (OD)
O
O
I
I
Function
HDLC-Interface Frame Synchronization
Channel A/B
Frame synchronization pulse in clock mode 2,
data strobe in clock mode 1.
HDLC-Interface Data Clock Channel A/B. Single
or double data rate.
Receive Serial Data HDLC-Channel A/B
The serial data received on this lines is forwarded
into the corresponding HDLC-receive channel.
Data is sampled on the
– falling edge of HDC (CCR2:RDS = 0) or
– rising edge of HDC (CCR2:RDS = 1).
Transmit Serial Data HDLC-Channel A/B.
Data output lines of the corresponding HDLC-
transmit channel. Depending on the bit
CCR1:ODS the pins have push pull or open
drain characteristic. When transmission is
disabled (TSCA or B = 1) or when bit
CCR2:TXDE is reset the pins are in the state
high impedance.
Tristate Control HDLC-Channel A/B, active low.
Supplies a control signal for an external driver.
When low the corresponding TxD-outputs are
valid. The detailed functionality is defined
programming the SACCO-registers
CCR2:SOC1,SOC0. During reset these lines are
high.
Collision Data HDLC-Channel A/B
In a bus configuration, the external serial bus must
be connected to the respective CxD-pin for
collision detection.
In point-to-point configurations the pin provides a
"clear to send" function. When '0'/'1' the transmit
channel is enabled/disabled. If this function is
not needed CxDA/B has to be tied to
20
PEB 20550
PEF 20550
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Overview
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