PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 142
PEF20550HV2.1XT
Manufacturer Part Number
PEF20550HV2.1XT
Description
Manufacturer
Infineon Technologies
Datasheet
1.PEF20550HV2.1XT.pdf
(407 pages)
Specifications of PEF20550HV2.1XT
Lead Free Status / Rohs Status
Compliant
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CDS2..0
CUS3..2
4.6.11 Configurable Interface Bit Shift Register (CBSR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: 00
Semiconductor Group
bit 7
0
CFI-Downstream bit Shift 2..0.
From the zero offset bit position (CBSR = 20
and upstream) can be shifted by up to 6 bits to the left (within the time slot
number TSN programmed in CTAR) and by up to 2 bits to the right (within
the previous time slot TSN – 1) by programming the CBSR:CDS2..0 bits:
CBSR:CDS2..0
000
001
010
011
100
101
110
111
The bit shift programmed to CBSR:CDS2..0 affects both the upstream and
downstream frame position in the same way.
CFI-Upstream bit Shift 3..0.
These bits shift the upstream CFI-frame relative to the downstream frame by
up to 15 bits. For CUS3..0 = 0000, the upstream frame is aligned with the
downstream frame (no bit shift).
CDS2
H
CDS1
CDS0
Time Slot No.
TSN – 1
TSN – 1
TSN
TSN
TSN
TSN
TSN
TSN
142
CUS3
read/write
read/write
Detailed Register Description
H
CUS2
) the CFI-frame (downstream
Bit No.
1
0
7
6
5
4
3
2
address: 1A
address: 34
CUS1
PEB 20550
PEF 20550
bit 0
H
H
CUS0
01.96
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