PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 147

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

and downstream memory blocks. Bits MA6..0 encode the CFI- or PCM-port and time slot
number as in the following tables:
Table 19
Time Slot Encoding for Data Memory Accesses
PCM-mode 1,3
PCM-mode 2
4.6.14 Memory Access Address Register (MAAR)
Access in demultiplexed P-interface mode:
Access in multiplexed P-interface mode:
Reset value: xx
The Memory Access Address Register MAAR specifies the address of the memory
access. This address encodes a CFI time slot for control memory (CM) and a PCM time
slot for data memory (DM) accesses. Bit 7 of MAAR (U/D-bit) selects between upstream
PCM-mode 0
Semiconductor Group
bit 7
U/D
MA6
H
MA5
bit U/D
bits MA6..MA3, MA0
bits MA2..MA1
bit U/D
bits MA6..MA3, MA1, MA0
bit MA2
bit U/D
bits MA6..MA0
Data Memory Address
MA4
147
MA3
read/write
read/write
Detailed Register Description
MA2
direction selection
time slot selection
logical PCM-port number
direction selection
time slot selection
logical PCM-port number
direction selection
time slot selection
address: 01
address: 02
MA1
PEB 20550
PEF 20550
bit 0
H
H
MA0
01.96