PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 306

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

In IOM-2 applications, however, (active handshake protocol), it is also possible that a
slave device requests a data transfer e.g. when an IEC-Q device has received an EOC
message over the U interface.
For these applications the ELIC has implemented a search mechanism that looks for
active handshake bits. When such a monitor channel is found, the P is interrupted
(ISTA_E:MAC) and the address of the involved MF channel is stored in a register
(MFAIR). The MF handler can then be pointed to that channel by copying the contents
of MFAIR to MFSAR and the actual message transfer can take place.
5.5.3.1 Registers used in Conjunction with the MF Handler
In detail, the following registers are involved when performing MF channel transfers:
Operation Mode Register
OMDR:
MFPS:
Monitor/Feature Control Channel FIFO
MFFIFO:
The 16 byte bidirectional MFFIFO provides intermediate storage for data bytes to be
transmitted or received over the monitor or feature control channel.
Note: The data transfer over an MF channel is half-duplex i.e. if a ‘transmit + receive’
MFD7 … 0:
Semiconductor Group
command is issued, the transmit section of the transfer must first be completed
before the receive section starts.
bit 7
bit 7
OMS1
MFD7
MF channel Protocol Selection;
MFPS = 0: Handshake facility disabled; to be used for SLD and
MFPS = 1: Handshake facility enabled; to be used for IOM-2
MF Data bits 7 … 0; MFD7 (MSB) is the first bit to be sent over the
serial CFI, MFD0 (LSB) the last.
OMS0
MFD6
IOM-1 applications.
applications.
MFD5
PSB
read/write
MFD4
PTL
306
read/write reset value:
MFD3
COS
reset value:
MFPS
MFD2
Application Hints
MFD1
CSB
00
empty
PEB 20550
PEF 20550
H
bit 0
bit 0
MFD0
RBS
01.96