PEF20550HV2.1XT Infineon Technologies, PEF20550HV2.1XT Datasheet - Page 164

• Manufacturer Part Number: PEF20550HV2.1XT
• Manufacturer: Infineon Technologies

Specifications of PEF20550HV2.1XT

• Lead Free Status / Rohs Status: Compliant

4.7.2
Access in demultiplexed
respectively. The DMA-controller must take care to perform the last DMA-transfer. If it is
missing, the DRQTA/B-line will go active again when CSS is raised.
Additionally an RME-interrupt is issued after the last byte has been transferred. As a
result, the DMA-controller may transfer more bytes as actually valid in the current
received frame. The valid byte count must therefore be determined reading the registers
RBCH, RBCL following the RME-interrupt.
The corresponding DRQRA/B pin remains "high" as long as the RFIFO requires data
transfers. It is deactivated upon the rising edge of the 31st DMA-transfer or, if n < 32 or n
is the remainder of a long frame, upon the falling edge of the last DMA-transfer.
If n
line will go high again as soon as CSS goes high, thus indicating further bytes to fetch.
Access in multiplexed
Reset value: xx
TD7..0
Interrupt controlled data transfer (interrupt mode, selected if DMA-bit in register
XBCH is reset).
Up to 32 bytes of transmit data can be written to the XFIFO following an XPR-interrupt.
DMA controlled data transfer (DMA-mode, selected if DMA-bit in register XBCH is
set).
Prior to any data transfer, the actual byte count of the frame to be transmitted must be
written to the registers XBCH, XBCL:
If a data transfer is then initiated via the CMDR-register (commands XPD/XTF or XDD),
the SACCO autonomously requests the correct amount of block data transfers (n 32 +
remainder, n = 0,1, …).
The corresponding DRQTA/B pin remains "high" as long as the XFIFO requires data
transfers. It is deactivated upon the rising edge of WR in the DMA-transfer 31 or n
Semiconductor Group
bit 7
P-interface mode:
P-interface mode:
TD7
32 and the DMA-controller does not perform the 32nd DMA-cycle, the DRQRA/B-
1 byte: XBCL = 0
n bytes: XBCL = n
Transmit FIFO (XFIFO)
Transmit Data 7…0, data byte to be transmitted on the serial interface.
TD6
H
TD5
1
write
write
TD4
address (Ch-A/Ch-B): 00
address: (Ch-A/Ch-B): 00
164
TD3
Detailed Register Description
TD2
H
H
..1F
..3E
TD1
H
H
/40
/B0
PEB 20550
PEF 20550
H
H
..5F
bit 0
..BE
TD0
H
H
01.96
1