EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 101

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Table 41. SPI Transmit Shift Register
SPI Receive Buffer Register
Table 42. SPI Receive Buffer Register
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
TX_DATA
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
RX_DATA
The SPI Receive Buffer register (SPIx_RBR) is used by the SPI slave to receive data from
the serial bus. A write to the (SPIx_TSR) register initiates reception of another byte, and
only occurs in the master device. When you read the SPIx_RBR register, a buffer is being
read. The first SPIF bit must be cleared by the time a second transfer of data from the shift
register is initiated or an OVERRUN condition exists. Should an overrun occur, the byte
causing the overrun is lost.
The SPI Receive Buffer Read Only registers share the same address space as the SPI
Transmit Shift Write Only registers.
Value Description
00h–
FFh
Value Description
00h–
FFh
W
SPI data transmission.
SPI data reception.
X
X
R
7
7
W
X
X
R
6
6
W
X
X
R
5
5
(SPI0_TSR = B8h, SPI1_TSR = BCh)
(SPI0_RBR = B8h, SPI1_RBR = BCh)
W
R
X
X
4
4
W
R
X
X
3
3
W
R
X
X
2
2
Product Specification
Serial Peripheral Interface
W
R
X
X
1
1
W
X
X
R
0
0
eZ80190
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