EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 106

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Arbitration
Clk1 Signal
Clk2 Signal
SCL Signal
A master may start a transfer only if the bus is free. Two or more masters may generate a
START condition within the minimum hold time of the START condition. The result is a
defined START condition to the bus. Arbitration occurs on the SDA line while the SCL
line is at the High level in such a way that the master, (which transmits a High level while
another master is transmitting a Low level), switches off its data output stage. The master
switches off its data output stage because the level on the bus does not correspond to its
own level.
Arbitration can continue for many bits. Its first stage is a comparison of the address bits. If
the masters are each trying to address the same device, arbitration continues with a com-
parison of the data. Because address and data information on the I
tration, no information is lost during this process. A master which loses the arbitration can
generate clock pulses until the end of the byte in which it loses the arbitration.
If a master also incorporates a slave function and it loses arbitration during the addressing
stage, it is possible that the winning master is trying to address it. The losing master must
switch over immediately to SLAVE RECEIVE mode.
procedure for two masters. Of course, more may be involved (depending on how many
masters are connected to the bus). The moment there is a difference between the internal
data level of the master generating DATA 1 and the actual level on the SDA line, its data
output is switched off, which means that a High output level is then connected to the bus.
As a result, the data transfer initiated by the winning master is not affected. Because con-
trol of the I
there is no central master, nor any order of priority on the bus.
Special attention must be paid if, during a serial transfer, the arbitration procedure is still
in progress at the moment when a repeated START condition or a STOP condition is trans-
mitted to the I
must send this repeated START condition or STOP condition at the same position in the
format frame.
2
C bus is decided solely on the address and data sent by competing masters,
2
C bus. If it is possible for such a situation to occur, the masters involved
Figure 20. Clock Synchronization In I
Counter
Reset
Wait State
Figure 20
2
Start Counting
C Protocol
High Period
Product Specification
displays the arbitration
2
C bus is used for arbi-
I2C Serial I/O Interface
96