EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 80

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

UART Interrupts
PS006614-1208
UART Transmitter Interrupt
UART Receiver Interrupts
There are five different sources of interrupts from the UART. These five sources of inter-
rupts are:
1. Transmitter
2. Receiver (three different interrupts)
3. Modem status
The transmitter interrupt is generated if there is no data available for transmission. This
interrupt can be disabled using the individual interrupt enable bit, or cleared by writing
data into the UARTx_THR register.
A receiver interrupt can be generated by three possible events. The first event, a receiver
data ready interrupt event, indicates that one or more data bytes were received and are
ready to be read. If the FIFO is enabled, and the trigger level is set, then this interrupt is
generated if the number of bytes in the receive FIFO is greater than or equal to the trigger
level. If the FIFO is not enabled, the interrupt is generated if the receive buffer contains a
data byte. This interrupt is cleared by reading the UARTx_RBR.
The second interrupt source is the receiver time-out. A receiver time-out interrupt is gen-
erated when there are fewer data bytes in the receive FIFO than the trigger level. There are
no READs and writes to or from the receive FIFO for four consecutive byte times. After
the receiver time-out interrupt is generated, it is cleared only after it empties the entire
receive FIFO.
The first two interrupt sources from the receiver (data ready and time-out) share an inter-
rupt enable bit.
The third source of a receiver interrupt is a line status error indicating an error in byte
reception. This error may result from:
•
•
•
•
An interrupt due to one of the above conditions is cleared when the UARTx_LSR register
is read. In the case of FIFO mode, a line status interrupt is generated only after the
received byte with an error reaches the top of the FIFO and is ready to be read.
Incorrect received parity
Incorrect framing (the stop bit is not detected by the receiver at the end of the byte)
Receiver overrun condition
A Break Indication being detected on the receive data input
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80190
70