EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 84

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
UART Interrupt Enable Register
Table 28. UART Interrupt Enable Registers
Bit
Position
[7:0]
RXD
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:4]
3
MIIE
2
LSIE
1
TIE
0
RIE
The UARTx_IER register, listed in
rupts. The UARTx_IER registers share the same I/O addresses as the BRGx_DLR_H reg-
isters.
Value
00h–
FFh
Value
0000
0
1
0
1
0
1
0
1
Description
Receive data byte.
R/W
Description
Reserved
The modem interrupt on edge detect of status inputs is
disabled.
The modem interrupt on edge detect of status inputs is
enabled.
The line status interrupt is disabled.
The line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or
break detection.
The transmit interrupt is disabled.
The transmit interrupt is enabled. An interrupt is generated
when the transmit FIFO buffer is empty indicating no bytes are
available for transmission.
The receive interrupt is disabled.
The receive interrupt and receiver time-out interrupt are
enabled. An interrupt is generated if the FIFO buffer contains
data ready for a READ or if the receiver times out.
7
0
R/W
6
0
R/W
Table
5
0
28, is used to enable and disable UART inter-
R/W
(UART0_IER = C1h, UART1_IER = D1h)
4
0
Universal Asynchronous Receiver/Transmitter
R/W
3
0
R/W
2
0
Product Specification
R/W
1
0
R/W
0
0
eZ80190
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