EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 55

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
GPIO Mode 6—
falling edge on the pin cause an interrupt request to be sent to the CPU. Writing a 1 to the
Port x Data register bit position resets the corresponding interrupt request. Writing a 0 pro-
duces no effect. The programmer must set the Port x Data register before entering the dual-
edge-triggered interrupt mode.
GPIO Mode 7—
alternate functions assigned to the pin. For example, the alternate mode function for PC7
is RI1. When GPIO Mode 7 is enabled, the pin output data and pin tristate control come
from the alternate function's data output and tristate control, respectively. The value in the
Port x Data register produces no effect on operation.
For Ports A and B, which do not feature alternate I/O functions, selecting GPIO Mode 7
results in a configuration of the pins for input from the pin and high-impedance output as
in GPIO Mode 2.
GPIO Mode 8—
rupt request is generated when the level at the pin is the same as the level stored in the
Port x Data register. The port pin value is sampled by the system clock. The input pin must
be held at the selected interrupt level for a minimum of 2 clock periods to initiate an inter-
rupt. The interrupt request remains active as long as this condition is maintained at the
external source.
GPIO Mode 9—
value in the Port x Data register determines if a positive or negative edge causes an inter-
rupt request. A 0 in the Port x Data register bit sets the selected pin to generate an interrupt
request for falling edges. A 1 in the Port x Data register bit sets the selected pin to generate
an interrupt request for rising edges. The interrupt request remains active until a 1 is writ-
ten to the Port x Data register bit’s corresponding interrupt request. Writing a 0 produces
no effect on operation. The programmer must set the Port x Data register before entering
the single-edge-triggered interrupt mode.
A simplified block diagram of a GPIO port pin is displayed in
The bit enables a dual-edge-triggered interrupt mode. Both a rising and a
For Ports C and D, the port pin is configured to pass control over to the
The port pin is configured for level-sensitive interrupt modes. An inter-
The port pin is configured for single-edge-triggered interrupt mode. The
Figure 7
General-Purpose Input/Output
Product Specification
on page 46.
eZ80190
45