EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 140
![IC EZ80 ACCLAIM 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050SC00TR
Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Manufacturer
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- Download datasheet (4Mb)
PS006614-1208
MACC
Table 65. MACC y DATA Ending Address Register
MACC
Table 66. MACC y DATA Reload Address Register
MACC Control Register
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
MACC_yEND
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
MACC_yRELOAD
The MACC_yEND register, listed in
the MACC to read 16-bit values from the y DATA for performing its calculations.
The MACC_yRELOAD register, listed in
DATA of MACC RAM. When the y DATA address increments to the value in
MACC_yEND, the next y DATA address is taken from this MACC_yRELOAD register.
The MACC Control register, listed in
interrupt enable on completion of calculation. All writes to this register clear the 40-bit
accumulator to 0 (MACC_ACx =
y
y
DATA Ending Address Register
DATA Reload Address Register
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
R/W
7
0
7
0
Ending address for the y DATA of MACC RAM.
Reload address for the y DATA of MACC RAM.
R/W
R/W
6
0
6
0
00h
R/W
R/W
5
0
5
0
Table 65
Table
}.
Table
R/W
R/W
67, provides added MACC features including
4
0
4
0
on page 130, defines the ending address for
66, defines the reload address within the y
R/W
R/W
3
0
3
0
(MACC_yRELOAD = E6h)
(MACC_yEND = E5h)
R/W
R/W
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
Multiply-Accumulator
R/W
R/W
0
0
0
0
eZ80190
130
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