EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 50

IC EZ80 ACCLAIM 50MHZ 100LQFP

EZ80190AZ050SC00TR

Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet

Specifications of EZ80190AZ050SC00TR

Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80190AZ050SC00TR
Manufacturer:
Zilog
Quantity:
10 000
WDT Operation
WDT Registers
PS006614-1208
Enabling And Disabling The WDT
Time-Out Period Selection
RESET Or NMI Generation
WDT Control Register
The WDT is disabled upon a system RESET. To enable the WDT, the application program
must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the WDT can-
not be disabled without a system RESET.
There are four choices of time-out periods for the WDT—2
clock cycles. With a 50 MHz crystal oscillator, the available WDT time-out periods are
approximately 5.24 ms, 83.9 ms, 671 ms, and 2.68 s. The WDT time-out period is defined
by the WDT_PERIOD field of the WDT_CTL register (WDT_CTL[1:0]).
Upon a WDT time-out, the RST_FLAG bit in the WDT_CTL register is set to 1. In addi-
tion, the WDT can cause a system RESET or send a nonmaskable interrupt (NMI) signal
to the CPU. The default operation is for the WDT to cause a system RESET. The reset
pulse generated by a WDT time-out is 64 clock cycles wide. It asserts/deasserts on the ris-
ing edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the
source of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT
asserts an NMI for CPU processing. The RST_FLAG bit can be polled by the CPU to
determine the source of the NMI event.
The WDT Control register, listed in
used to enable the WDT, set the time-out period, indicate the source of the most recent
RESET, and select the required operation upon WDT time-out.
Table 10
on page 41, is an 8-bit Read/Write register
18
, 2
22
Product Specification
, 2
25
, and 2
Watchdog Timer
27
system
eZ80190
40

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