EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 155

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Table 79. DMA Byte Count Registers DMA0_BC_L = F4h, DMA0_BC_H = F5h, DMA1_BC_L =
DMA Control Registers
Table 80. DMA Control Registers
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DMAX_BC_L
or
DMAX_BC_H
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
DMA_EN
6
IRQ_DMA
5
4
BURST
Table 80
accessed by the CPU using I/O instructions.
lists the control registers used by the DMA controller. These registers are
Value Description
00h–
FFh
Value Description
0
1
0
1
0
0
1
R/W
R/W
7
0
7
0
The 2 pairs of DMA Byte Count registers contain the
number of bytes to be transferred during the current
operation. The 16-bit byte count values are returned by
{DMAx_BC_H, DMAx_BC_L}, where x is either 0 or 1.
The DMA channel is disabled. This bit must be reset to 0
by the software to remove DMA interrupt service requests.
The DMA channel is enabled. This bit is not reset to 0
following completion of a DMA transfer.
The interrupt is disabled for this DMA channel.
The interrupt is enabled for this DMA channel.
Reserved—must be 0.
The DMA is configured for CYCLE-STEAL mode.
The DMA is configured for BURST mode.
R/W
R/W
FDh, DMA1_BC_H = FEh
6
0
6
0
R/W
R/W
5
0
5
0
(DMA0_CTL = F6h, DMA1_CTL = FFh)
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
R/W
R/W
Direct Memory Access Controller
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
eZ80190
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