EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 116

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Table 50. I
I
Table 51. I
I
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SLAX
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
DATA
2
2
C Control Register
C Data Register
The I
mitted or the data byte just received. In MASTER TRANSMIT or SLAVE TRANSMIT
modes, the msb of the byte is transmitted first. In MASTER RECEIVE or SLAVE
RECEIVE modes, the first bit received is placed in the msb of the register. After each byte
is transmitted, the I2Cx_DR register contains the byte that is present in the event of lost
arbitration.
The I2Cx_CTL register, listed in
interrupts and the master slave relationships on the I
When the Interrupt Enable bit (IEN) is set to 1, the interrupt line goes High when the IFLG
is set to 1. When IEN is cleared to 0, the interrupt line always remains Low.
2
2
C Extended Slave Address Registers
C Data Registers
2
C Data Register, listed in
Value Description
00h–
FFh
Value Description
00h–
FFh
R/W
R/W
Least significant 8 bits of the 10-bit extended slave address.
I
7
0
7
0
2
C data byte.
R/W
R/W
6
0
6
0
Table
Table 52
R/W
R/W
5
0
5
0
51, contains the data byte/slave address to be trans-
(I2C0_DR = CAh, I2C1_DR = DAh)
is a control register that is used to control the
R/W
R/W
4
0
4
0
(I2C0_xSAR = C9h, I2C1_xSAR = D9h)
R/W
R/W
2
3
0
3
0
C bus.
R/W
R/W
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
I2C Serial I/O Interface
R/W
R/W
0
0
0
0
106