EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 126

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Defining a New Calculation as READY
Defining the DATA Bank as EMPTY
instruction. Depending upon the number of bytes of result required, the INI2R instruction
can read all 5 of the MACC_ACx registers or as few as 1.
The Multiply-Accumulator decodes its I/O addresses from ADDR[7:0]. In addition, it
monitors ADDR[15:8] to detect the final transfer of a block using the OTI2R or INI2R
instructions. These instructions drive the value in the CPU’s B register onto ADDR[15:8]
and the value in the CPU’s C register onto ADDR[7:0]. The B register decrements after
completion of each transfer in the OTI2R or INI2R block transfer. The C register incre-
ments after completion of each transfer. The final transfer occurs when B contains the
value of
nates. For more information on these CPU instructions and CPU registers refer to eZ80
CPU User Manual (UM0077).
When writing a new calculation to the MACC control registers, any of the following
actions change the state of the DATA bank from EMPTY to READY:
•
•
•
If the MACC is prepared to begin a new calculation (CALC bank status is EMPTY or
DONE), the banks are immediately swapped as soon as the new calculation defined in the
DATA bank is READY. When this swap occurs, the CALC bank status becomes IN
PROGRESS.
Defining the DATA Bank as EMPTY indicates completion of a result read operation.
When reading a result from the MACC Accumulator registers, any of the following
actions change the state of the DATA bank from DONE to EMPTY:
•
•
A write to MACC_AC4, the MSB of the MACC Accumulator.
A write to MACC_CTL with ADDR[15:8] =
write requirement during its final transfer)
–
A write to MACC_AC0, MACC_AC1, MACC_AC2, or MACC_AC3 with
ADDR[15:8] =
final transfer)
A read from MACC_AC4, the MSB of the MACC Accumulator
A read from MACC_AC0, MACC_AC1, MACC_AC2, or MACC_AC3 with
ADDR[15:8] =
This write also clears the MACC Accumulator
01h
. After this final transfer, B decrements to 0 and the block instruction termi-
01h
01h
, as in the final transfer, using an INI2R instruction
(an OTI2R instruction satisfies this write requirement during its
01h
(an OTI2R instruction satisfies this
Product Specification
Multiply-Accumulator
eZ80190
®
116