EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 25
![IC EZ80 ACCLAIM 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050SC00TR
Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 1. 100-Pin LQFP Pin Identification of the eZ80190 Device (Continued)
PS006614-1208
Pin
No.
68
69
Symbol
PC1
MOSI1
RxD1
SDA1
PC2
SCK1
RTS1
Function
GPIO Port C
Master Out
Slave In
Receive Data
I
GPIO Port C
SPI Serial
Clock
Request to
Send
2
C Serial Data Input/Output
Signal Direction
Input/Output
Input/Output
Input
Input/Output
Input/Output
Output, Active Low The RTS1 pin carries the modem-control signal
Description
The PC1 pin can be used for GPIO. It can be
individually programmed as an input or output
and can also be used individually as an interrupt
input. Each Port C pin, when programmed as an
output, can be selected to be an open-drain or
open-source output. Port C is multiplexed with
one channel of the UZI interface.
The MOSI line is configured as an output when
the eZ80190 device is an SPI master device and
as an input when the eZ80190 device is an SPI
slave device. This signal is multiplexed with PC1.
The RxD1 pin is used by the UART to receive
asynchronous serial data. This signal is
multiplexed with PC1.
The SDA1 pin carries the I
signal is multiplexed with PC1.
The PC2 pin can be used for GPIO. It can be
individually programmed as an input or output
and can also be used individually as an interrupt
input. Each Port C pin, when programmed as an
output, can be selected to be an open-drain or
open-source output. Port C is multiplexed with
one channel of the UZI interface.
SPI serial clock. This signal is multiplexed with
PC2.
from the UART. This signal is multiplexed with
PC2.
Product Specification
2
C data signal. This
Architectural Overview
15
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