EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 87
![IC EZ80 ACCLAIM 50MHZ 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050SC00TR
Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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PS006614-1208
UART Line Control Register
Table 32. UART Line Control Registers
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
DLAB
6
SB
5
FPE
4
EPS
These registers, listed in
ters.
Table 33
Value
0
1
0
1
0
1
0
1
on page 78 lists character length and stop bit parameters.
R/W
Description
Access to the UART registers at I/O addresses C0h, C1h, D0h
and D1h is enabled.
Access to the Baud Rate Generator registers at I/O addresses
C0h, C1h, D0h and D1h is enabled.
Do not send a break signal.
Send Break
UART sends a continuous 0 on the transmit output from the
next following bit boundary. The transmit data in the transmit
shift register is ignored. After assigning this bit High, the TXD
output is made 0 only after the bit boundary is reached. Just
before assigning a 0 to TXD, it clears the transmit FIFO one
time. Any new data written to the transmit FIFO during a break
should be written only after the THRE bit of the UARTx_LSR
register goes High. This new data is transmitted after the UART
recovers from the break. After the break is removed, the UART
recovers from break for the next BRG edge.
Do not force a parity error.
Force a parity error. When this bit and the party enable bit
(PEN) are both 1, an incorrect parity bit is transmitted with the
data byte.
Use odd parity for transmission. The total number of 1 bit in the
transmit data plus parity bit is odd.
Use even parity for transmission. The total number of 1 bit in
the transmit data plus parity bit is even.
7
0
Table
R/W
6
0
32, are used to control the communication control parame-
R/W
5
0
(UART0_LCTL = C3h, UART1_LCTL = D3h)
R/W
4
0
Universal Asynchronous Receiver/Transmitter
R/W
3
0
R/W
2
0
Product Specification
R/W
1
0
R/W
0
0
eZ80190
77
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