EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 103

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Transferring Data
PS006614-1208
Data Validity
START and STOP Conditions
Byte Format
SDA Signal
SCL Signal
SDA Signal
SCL Signal
The data on the SDA line must be stable during the High period of the clock. The High or
Low state of the data line can only change when the clock signal on the SCL line is Low,
as displayed in
Within the I
STOP conditions, see
High indicates a START condition. A Low-to-High transition on the SDA line while SCL
is High defines a STOP condition.
START and STOP conditions are always generated by the master. The bus is considered to
be busy after the START condition. The bus is considered to be free at a defined time after
the STOP condition.
Every character transferred on the SDA line must be a single 8-bit byte. The number of
bytes that can be transmitted per transfer is unrestricted. Each byte must be followed by an
Start Condition
2
C bus protocol, unique situations arise which are defined as START and
Figure 17. START and STOP Conditions In I
Figure
S
Data Valid
Data Line
Stable
Figure 16. I
Figure
16.
17. A High-to-Low transition on the SDA line while SCL is
Data Allowed
Change of
2
C Clock and Data Relationship
Stop Condition
2
C Protocol
Product Specification
P
I2C Serial I/O Interface
93