EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 75

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PS006614-1208
Table 24. BRG Divisor Latch Registers—Low Byte
BRG Divisor Latch Registers—High Byte
Table 25. BRG Divisor Latch Registers—High Byte (BRG0_DLR_H = C1h, BRG1_DLR_H =
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:0]
BRG_DLR_L
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
The BRGx_DLR_L registers share the same address space with the UARTx_RBR and
UARTx_THR registers. Bit 7 of the associated UART Line Control register
(UARTx_LCTL) must be set to 1 to enable access for this register within each UZI device.
This register holds the High byte of the 16-bit divisor count loaded by the processor for
baud rate generation. The 16-bit clock divisor value is returned by {BRGx_DLR_H,
BRGx_DLR_L} where x is either 0 or 1 to identify the two available UZI devices. Upon
RESET, the 16-bit BRG divisor value resets to
must be between
proper operation is not guaranteed. Therefore, the minimum BRG clock divisor ratio is 2.
A write to either the Low- or High-byte registers for the BRG Divisor Latch causes both
bytes to load into the BRG counter, and causes the count to restart.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register for each UZI device. For more information see
Register
The BRGx_DLR_H registers share the same address space with the UARTx_IER regis-
ters. Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1
to enable access for this register within each UZI device.
Value
00h–
FFh
on page 77 (UARTx_LCTL).
0002h
R/W
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {BRG_DLR_H, BRG_DLR_L}.
R/W
7
0
7
0
and
R/W
R/W
6
0
6
0
FFFFh
R/W
R/W
because the values
5
0
5
0
D1h)
D0h
R/W
R/W
4
0
4
0
0002h
BRG0_DLR_L = C0h, BRG1_DLR_L =
R/W
R/W
3
0
3
0
. The initial 16-bit divisor value
0000h
R/W
R/W
2
0
2
0
and
Product Specification
0001h
UART Line Control
R/W
R/W
Universal Zilog Interface
1
0
1
0
are invalid, and
R/W
R/W
0
0
0
0
eZ80190
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