EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 114

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

I
PS006614-1208
2
C Registers
Addressing
Resetting the I
If the ACK bit is cleared to 0 during a transfer, the I
on SDA) after the next byte is received, and sets the IFLG bit. The
tains the status code
call address. The I
The processor interface provides access to six 8-bit registers: four Read/Write registers,
one Read Only register, and two Write Only registers. See
Table 48. I
Hardware Reset—When the I
I2Cx_SAR, I2Cx_xSAR, I2Cx_DR and I2Cx_CTL registers are cleared to
I2Cx_SR
Software Reset—Perform a software reset by writing any value to the I
Reset register (I2Cx_SRR). A software reset sets the I
STP, STA, and IFLG bits of the I2Cx_CTL register to 0.
Register
I2Cx_SAR
I2Cx_xSAR
I2Cx_DR
I2Cx_CTL
I2Cx_SR
I2Cx_CCR
I2Cx_SRR
Note: The lower case x in the register name can be either 0 or 1 depending upon which of the two
I 2 C devices are referenced within the eZ80190 device.
register is set to
2
C Register Descriptions
2
C Registers
2
C returns to the IDLE state when the IFLG bit is cleared to 0.
Description
Slave address register
Extended slave address register
Data byte register
Control register
Status register (Read Only)
Clock Control register (Write Only)
Software reset register (Write Only)
88h
or
F8h
98h
.
2
if SLAVE RECEIVE mode is entered with the general
C is reset by a hardware reset of the eZ80190 device, the
2
C transmits a NACK bit (High level
2
C back to the IDLE state and the
Table
Product Specification
48.
I2Cx_SR
I2C Serial I/O Interface
2
C Software
register con-
00h
. The
104