EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 73

• Manufacturer Part Number: EZ80190AZ050SC00TR
• Description: IC EZ80 ACCLAIM 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SC00TR

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Baud Rate Generator
PS006614-1208
Baud Rate Generator Functional Description
Recommended Usage of the Baud Rate Generator
mation. A description of the UZI Baud Rate Generator and the UZI control registers
appear in this chapter.
The Baud Rate Generator (BRG) is located within the UZI, but outside the three serial
communication controllers. The Baud Rate Generator creates a lower frequency clock
from the high-frequency system clock provided as an input to each UZI. Baud Rate Gener-
ator output is used as the clock source by the SPI and the UART. The I
its timing directly from the primary system clock.
The Baud Rate Generator consists of a 16-bit downcounter, two registers, and associated
decoding logic. The Baud Rate Generator’s initial value is defined by the two BRG Divi-
sor Latch registers, {BRGx_DLR_H, BRGx_DLR_L}. At the rising edge of each system
clock, the BRG decrements until it reaches the value
ing edge, the BRG reloads the initial value from {BRGx_DLR_H, BRGx_DLR_L) and
outputs a pulse to indicate the end-of-count. Calculate the BRG output frequency with the
following equation:
Upon RESET, the 16-bit BRG divisor value resets to
value of
the Low- or High-byte registers for the BRG Divisor Latch causes both the Low and High
bytes to load into the BRG counter, and causes the count to restart.
The divisor registers can only be accessed if bit 7 of the UART Line Control register
(UARTx_LCTL) is set to 1. After reset, this bit is reset to 0.
The following is the normal sequence of operations that should occur after the eZ80190
device is powered on to configure the UZI Baud Rate Generator:
•
•
•
BRGx Output Frequency =
Assert and deassert RESET
Set UARTx_LCTL[7] to 1 to enable access of the BRG divisor registers
Program the BRGx_DLR_L and BRGx_DLR_H registers
0001h
is also valid, and effectively bypasses the BRG. A software Write to either
{BRGx_DLR_H, BRGx_DLR_L}
System Clock Frequency
0001h
0002h
. On the next system clock ris-
. A minimum BRG divisor
Product Specification
Universal Zilog Interface
2
C device generates
eZ80190
63