EZ80190AZ050SC00TR Zilog, EZ80190AZ050SC00TR Datasheet - Page 63
EZ80190AZ050SC00TR
Manufacturer Part Number
EZ80190AZ050SC00TR
Description
IC EZ80 ACCLAIM 50MHZ 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 17. Register Values for Memory Chip Select Example (Continued)
I/O Chip Select Operation
PS006614-1208
Chip
Select
CS2
CS3
CSx_CTL[3]
CSx_EN
1
1
I/O Chip Selects can only be active when the CPU is performing I/O instructions. Because
the I/O space is separate from the memory space in the eZ80190 device, there can never be
a conflict between I/O and memory addresses.
The I/O Chip Select logic decodes 8 bits from the address bus, ADDR[11:4]. Because the
upper byte of the address bus, ADDR[23:16], is ignored, the I/O devices can always be
accessed from within any memory mode (ADL or Z80). The MBASE offset value used for
setting the Z80 MEMORY mode page is also always ignored.
Four I/O Chip Selects are available with the eZ80190 device. To generate a particular I/O
Chip Select, the following conditions must be met:
•
•
•
•
•
•
If all of the foregoing conditions are met to generate an I/O Chip Select, then the following
actions occur:
•
•
The Chip Select is enabled by setting CS_EN to 1
The Chip Select is configured for I/O by setting CS_IO to 1
An I/O Chip Select address match occurs—ADDR[11:4] = CSx_LBR[7:0]
No higher-priority (lower-number) Chip Select meets the above conditions
The lower byte of the I/O address is not within the on-chip peripheral address range of
80h
80h ≤ ADDR[7:0] ≤ FFh
An I/O instruction must be executing
A Chip Select—CS0, CS1, CS2, or CS3—is activated (driven Low)
The IORQ signal is activated (driven Low)
CSx_CTL[4]
to
CSx_IO
FFh
0
0
. On-chip peripheral registers assume priority for all addresses where
CSx_LBR CSx_UBR Description
A0h
D0h
CFh
FFh
CS2 is enabled as a Memory Chip Select.
Valid addresses range from A00000h to
CFFFFFh.
CS3 is enabled as a Memory Chip Select.
Valid addresses range from D00000h to
FFFFFFh.
Chip Selects and Wait States
Product Specification
eZ80190
53
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